Senior Signal Integrity Engineer, Platform

Senior Signal Integrity Engineer, Platform Location: Sunnyvale, CA, USA Level: Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment, utilizing Google labs, power, and safety equipment. Regular development and processing of engineering hardware must be performed on site. Required Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 4 years of experience working in a signal integrity technical environment, or 3 years of experience with an advanced degree. Preferred Qualifications Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field. 1 year of experience in technical leadership. Experience with the product development process for mass volume production design, with a focus on signal integrity, power integrity and lab validation. Experience with PCIE, DDR, SATA, ethernet standards, PCB, connector, or cable design and assembly processes, including materials and component selection. Experience with Allegro, HFSS, SIwave, ADS, Matlab, PowerDC, PowerSI, and scripting for data collection and analysis (e.g., Python, bash). Experience in a lab environment with Serializer/Deserializer (SerDes) testing and understanding of SerDes capabilities. About the Job Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational tests are complex and unique, enabled by custom hardware designed and made in-house. As a Signal Integrity Engineer, you will design and build the systems that are important to our largest and powerful computing infrastructure. You will see those systems from concepts all the way through to high volume manufacturing. You will support the machinery that goes into our data centers affecting millions of Google users. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $147,000-$216,000 plus bonus, equity and benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Responsibilities Support System Signal Integrity (SI) design on data center hardware products. Collaborate with board, chip and system engineers, design partners, and chip vendors, to support system SI design, explore layout and manufacturability tradeoffs, and ensure that product functions as required. Support Application‑Specific Integrated Circuit (ASIC), package, board, connector, and cable vendors to develop new interconnect technologies. Participate in system interconnects bring up and qualification, work with test engineers and configure chips to ensure adequate margin. Collaborate with design engineers, Printed Circuit Board (PCB) designers, and system teams to help solve SI issues. Equal Employment Opportunity Statement Google is a proud equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity and expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know Your Rights: Workplace Discrimination is Illegal, Belonging at Google, and How We Hire. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr Google Inc.