Tech Lead, RTL/SoC Design for AI Connectivity
Astera Labs
Astera Labs in San Jose, CA is seeking a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI infrastructure. You will own RTL design for critical blocks from microarchitecture through synthesis, collaborating with architecture, verification, DFT and physical design teams. The role emphasizes leadership, design methodology, and pre/post-silicon debugging, with opportunities to influence tapeout schedules and chip performance. #J-18808-Ljbffr Astera Labs
Vacancy posted 2 days ago
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