Controller
Cavendor
Cavendor is seeking a Verification Lead to own the verification strategy, planning, and execution for the Memory Controller subsystem, including CHI-G protocol compliance and DFI interface verification. This role leads a team of verification engineers through architecture updates driven by design changes to the memory controller. You will develop UVM-based testbenches and scoreboards, drive coverage closure and sign-off, coordinate RTL changes with design, and report progress to management. #J-18808-Ljbffr
Vacancy posted 1 day ago
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