Senior ASIC Physical Design Engineer

Cisco's Common Hardware Group (CHG) is looking for a seasoned Physical Design engineer to advance silicon for core Switching, Routing, and Wireless products. You’ll own RTL-to-GDSII flows, CTS, timing sign-off, and PPA optimizations across 7nm/5nm/3nm nodes. You will collaborate with RTL, DFT, and EDA teams, using Innovus, Primetime, and Calibre to enable best-in-class design methodology. Competitive salary and benefits in the U.S. are provided. #J-18808-Ljbffr Cisco