Design verification engineer

Title: Design Verification Engineer

Location: Remote anywhere in the USA and Canada

Duration: Full-time (REMOTE)




VISA: ONLY USC AND GC

JOB DESCRIPTION

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partnork and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we're eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

What you will do:

• Work on HVL (UVM / SystemVerilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flows.
• Perform constraint random verification, assertion writing, coverage analysis, debugging.
• Work with ARM cores, formal verification, SV DPI-C.
• What You Will Bring:
• Experience with verification tools such as UVM, SystemVerilog, and Verilog
• Strong understanding of semiconductor design and verification methodologies
• Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus.
• Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plus.