Senior Software R&D Engineer, ECO Route - VLSI EDA

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.NVIDIA's world-leading hardware relies on design exploration beyond the limits of conventional tools. Our team develops highly optimized internal EDA technology by combining novel algorithms, parallel computing, machine learning, and high-performance C++.We are seeking a Senior Software R&D Engineer to invent the next generation of detailed physical design algorithms, with a focus on ECO routing and physical optimization. These algorithms sit at the core of applications spanning extreme timing and power optimization, incremental logic synthesis, metal ECOs, precision clock-tree tuning, and high-speed interconnect.What you’ll be doing:Develop incremental physical-design technology that can rapidly implement high-performance logic changes with DRC and parasitic awareness, including for both all-layer and metal-only ECOs.Invent improved detailed-routing algorithms for the intricate mix of discrete and continuous optimization problems arising from DRC constraints in the latest manufacturing processes.Help craft cross-domain optimization tools that simultaneously consider logic, timing, clocks, testability, power distribution, placement, along with routing and DRCs to push the frontier of computing performance.Own problems end-to-end—from algorithm invention through implementation, validation, and production deployment.What we need to see:MS, PhD, or equivalent experience, with 5+ years of relevant experience.Strong expertise in C++, high-performance software architecture and algorithm development, including complexity, data structures, and memory efficiency.Deep understanding of detailed routing, including advanced design rules, pin access, route optimization, and DRC-aware implementation.Understanding of areas often impacted and co-optimized with ECOs, including clock distribution, DFT, and power delivery.Authorization to work on export controlled data arising in CPUs, GPUs, LPUs, and communication networks.Ways to stand out from the crowd:Familiarity with logic and physical co-optimization principles, including logic restructuring, technology mapping, and using SAT solvers.Experience with related physical-design areas such as placement, legalization, and IR drop reduction.Experience applying LLMs, reinforcement learning, GNNs, or other machine-learning techniques to physical design, combinatorial optimization, or algorithm-performance tuning.Are you passionate about tackling innovative algorithms that enable the fastest, most efficient AI hardware? We have the scale, compute resources, and direct collaboration with hardware teams that make that possible!Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until September 4, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa Clara; US, TX, AustinType: Full time