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Senior Principal C++ Engineer - FPGA Prototyping & Timing Tech

$154k - $286k

Cadence Design Systems

Cadence Design Systems is seeking a Senior Principal C++ Software Engineer in San Jose, California. The ideal candidate will enhance our FPGA-Based Prototyping product, requiring strong experience in software development and timing analysis. With responsibilities including designing algorithms and improving timing flows, the position demands expertise in C/C++ programming and a solid understanding of EDA software. The annual salary ranges between $154,000 to $286,000, along with opportunities for bonuses and comprehensive benefits. #J-18808-Ljbffr

Vacancy posted 3 hours ago
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