AI XPU Architect: High-Performance Chip Design & Inference

Conductor is seeking an XPU Architect to own the compute engine architecture for the A-0 and A-1 systems in Austin, TX. The role involves leveraging existing 3rd party IP creatively to address bandwidth and memory interface challenges. The ideal candidate will have deep expertise in AI workloads, low latency LLM inference, and silicon implementation constraints, with a track record of owning high‑performance ASIC projects. Future generations will be semi-custom and custom designs. #J-18808-Ljbffr Conductor