Senior Static Timing Analysis (STA) Methodology Engineer

We are seeking a Senior STA Methodology Engineer to join our ASIC design team. In this role, you will own cross-functional timing methodology efforts across multiple IPs, projects, and technology nodes for our cutting‑edge SoC designs targeting 5G, IoT, and LEO satellite communication applications. You will architect and maintain production STA flows, drive signoff closure, and introduce data-driven techniques to continuously improve PPA and team productivity.

WHAT YOU WILL BE DOING:

Lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes Develop and enhance STA methodologies across the full RTL-to-GDS flow, including early timing estimation, feasibility checks, synthesis and place-and-route optimization, signoff criteria, and post-route ECO strategies Architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA and runtime efficiency Drive signoff correlation and closure using PrimeTime and related tools (PT‑SI, PTPX, PT‑ECO) Debug timing constraints, resolve timing correlation issues, and develop effective timing closure strategies Explore and deploy data-driven and ML-assisted techniques to improve STA automation, predict and prioritize timing risk, and guide optimization across blocks and full-chip Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity Continuously refine workflows and introduce new technologies to ensure robust, PPA‑optimized timing solutions across all product lines Provide timing closure guidance and mentorship to design and physical design engineers

WHAT YOU BRING TO THIS ROLE:

BS or MS in Electrical or Computer Engineering, or equivalent industry experience 8+ years of industry experience in STA and timing methodology, focused on high-performance and low-power designs at advanced technology nodes Deep knowledge of STA tools and techniques, including noise, crosstalk, OCV, AOCV, POCV, and LVF analysis Fluency with PrimeTime and related signoff tools (PT‑SI, PTPX, PT‑ECO), with extensive hands‑on experience driving signoff correlation and closure Strong expertise in debugging timing constraints and resolving timing correlation issues across complex SoC designs Experience with MMMC analysis, timing ECO flows, and late-stage timing closure techniques Proficiency in writing robust, production-quality scripts in Tcl, Python, and/or Perl for CAD utilities and flow components Solid knowledge of clock tree synthesis (CTS) and its interaction with timing analysis Excellent communication and collaboration skills for cross-functional, multi-project environments

BONUS POINTS:

Experience with advanced process nodes (7nm, 5nm, or below) Familiarity with low-power design methodologies and their timing implications (DVFS, power gating) Exposure to interface protocol timing (DDR, PCIe, USB, SerDes) Experience applying ML or data-driven methods to EDA flow optimization Background in satellite communication, 5G, or IoT SoC design This is a full time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role. #J-18808-Ljbffr Dormont Manufacturing Co