R&D Process Engineer - Wafer Wet Process Engineer

Overview

The High Frequency Technology Center (HFTC) is seeking an R&D Process Engineer to develop, maintain and optimize manufacturing processes to fabricate passive interposer substrates for Keysight’s Heterogeneous Integration technology. This position is onsite at Keysight Headquarters in Santa Rosa, CA. Live in beautiful Sonoma County amongst vineyards, redwood forests, rivers, lakes and coastline while working on state-of-the-art advanced packaging technologies.

Responsibilities

The Process Engineer will own process development and process control to meet quality and production metrics. Responsibilities include a combination of R&D and manufacturing in partnership with Design, Integration, Test, Operations, Maintenance, Product and Failure Analysis teams. The Process Engineer is accountable for yield, cycle time, throughput, and quality of their process. This role involves technical depth in semiconductor processing, strong hands‑on aptitude, and effective communication and teamwork to meet department-level objectives.

Process Development Engineers at HFTC are responsible for process development and sustaining customized, cutting‑edge, micro and nano‑fabrication technologies. The focus of this position is process development, manufacturing sustainability, and R&D support for new product introductions, with specialization in wafer fab processes.

Key Responsibilities

• Deep knowledge and expertise with wafer process development in one or more of the following areas in order of preference: Chemical Mechanical Planarization (CMP), Solvent Stripping, Wet Etch, Electroplating.
• Own and advance performance across wet processes, CMP, Etch/Clean, Strip and Plating by driving quality, chamber health, defect reduction, yield improvement and overall process robustness through structured DOEs.
• Collaborate with equipment engineering on tool performance optimization, preventive‑maintenance strategies, throughput enhancements, and new tool installs or upgrades.
• Drive process control and stability through SPC charting, daily reviews, root‑cause analysis, and corrective actions using statistical tools (e.g., JMP).
• Work closely with other process integration, product, and circuit design engineers to define process and performance targets.
• Define process flows, develop new processes and drive continuous process improvement (CPI) efforts to maximize product yield.
• Report process metrics, root cause investigations, and process change implementations at the department level.
• Ensure successful process hand‑off to manufacturing partners.
• Work with Operations to implement robust process control and support production processes; diagnose and resolve process problems with urgency.
• Lead capital equipment acquisition projects that include tool evaluation, characterization, process development, and qualification.
• Have broader experience in upstream and downstream processes and the ability to understand process interactions.

Qualifications

• M.S. or Ph.D. in Materials Science, Chemical Engineering, Physics, Chemistry, or related fields.
• 5+ years of professional, hands‑on experience as process engineer with development and/or maintaining semiconductor wet processes and equipment.
• Knowledge of hardware systems to carry process steps, in the following order of preference: CMP, Solvent Stripping, Wet Etch, Electroplating, or similar wet processes.
• Familiarity with systems handling chemicals, such as pumps, flow monitoring and control, filters, CMP‑specific systems and chamber‑hardware configurations.
• Strong problem‑solving skills for measurement anomalies and tool‑drift issues.
• Experience with statistical process control (SPC) and design of experiments (DOE) is required.
• Academic experience will be considered in addition to industry experience if proven to attain the techniques of interest.
• Strong problem‑solving and analytical skills as well as excellent interpersonal and communication skills for cross‑functional interactions.
• Strong accountability, self‑initiative and proactive attitude are required for success.

Candidates must be local or willing to relocate to Santa Rosa, CA.

Applicants must be a U.S. citizen or lawful permanent resident of the U.S., or a protected individual, having authorization from the U.S. government for export‑controlled items under 8 U.S.C. 1324b(a)(3).

Equal Opportunity Employment

Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.

Compensation and Benefits

California Pay Range: MIN $138,960 - MIDPT $185,280 - MAX $231,600

This role is eligible for Keysight Results Bonus Program.

US Employees may be eligible for the following benefits:

• Medical, dental and vision
• Health Savings Account
• Health Care and Dependent Care Flexible Spending Accounts
• Life, Accident, Disability insurance
• Business Travel Accident and Business Travel Health
• 401(k) Plan
• Flexible Time Off, Paid Holidays
• Paid Family Leave
• Discounts, Perks
• Tuition Reimbursement
• Adoption Assistance
• ESPP (Employee Stock Purchase Plan)

Location

This position is at our Headquarters in Santa Rosa, CA.