Physical Design Lead

We are seeking a seasoned Physical Design Lead with expertise or significant interest in handling complete Physical Design for a complex Chiplet. You have had significant success driving Full Chip Floorplan based on architecture, Defining Timing targets across PVT's, drive for Full Chip PnR and Tile PnR closure and monitor Signoff functions like Physical Verification, IREM etc., This role also stretch you as a overall PD lead to work with IP teams, Architecture, Package and CAD/Methodology teams.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Own the Physical Design for one complete Chiplet on advanced technology nodes preferably TSMC 2nm or 3nm or 5nm.
• Work with all external stakeholders like Architects, IP teams, CAD/Methodology teams and all internal PD stakeholders like FCFP, FCT, TilePnR, PV from technical standpoint
• Signoff the Chiplet for Tapeout from Physical Design aspect

PREFERRED EXPERIENCE:

• 15+ years of experience in Physical Design handling full chip activities and signoff
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred