AI Compiler Engineer

Grow with us AI Compiler Engineer — Research Team Austin, Texas This is not a remote work opportunity. MLIR Architecture | Compiler Infrastructure | 5G/6G Silicon | Bare-Metal AI The Mission Most AI compiler engineers optimize models for GPUs that already exist. You will optimize them for silicon that hasn’t yet been built. As our Senior AI Compiler Engineer, you’ll build a complete MLIR‑based compiler stack from scratch, purpose‑built to run massive AI models such as Llama 3 on bare‑metal 5G/6G telecommunications silicon, where there is no OS and every byte of memory must be accounted for. The gap between a research model and hardware‑optimized silicon execution is one of the most technically brutal problems in the industry. You will be the engineer who closes it. What You’ll Actually Be Doing MLIR Architecture — Own the Stack Design and implement custom MLIR dialects from scratch, including TableGen definitions, transformation passes, and the dialect conversion infrastructure that bridges high‑level AI graphs to custom silicon. This is greenfield compiler work at its most consequential. Lowering & Legalization — Zero Tolerance for Approximation Lower high‑level computational graphs exported from JAX and StableHLO into hardware‑specific IR, preserving every bit of mathematical fidelity. Concurrency & Memory Modeling — Orchestrate the Machine Build static scheduling and tiling passes that choreograph data movement between HBM and on‑chip local memory without virtual memory, garbage collection, or safety nets. Production C++ — Code That Ships to Silicon Maintain a high‑performance, modular, LLVM‑based compiler codebase where correctness and determinism are mandatory. Join our Team What You Bring MLIR Mastery — You’ve built custom passes and dialect conversions, written TableGen definitions, and navigated the full complexity of the MLIR framework in a real production context. Compiler Fundamentals — You possess deep, hands‑on C++ and LLVM expertise, including IR structure, pass pipelines, and code generation pipelines that ship. Framework Integration — You’ve exported and lowered real models from JAX, PyTorch, or TensorFlow, understanding the gap between a research checkpoint and a deployable IR. Dialect Expertise — You know StableHLO or XLA at the op‑semantics level, not just the API surface. What Makes You Exceptional Experience targeting Embedded DSP or VLIW architectures— instruction scheduling, register pressure, and related work. Advanced optimization depth: loop tiling, vectorization, quantization lowering, fixed‑point arithmetic. Hardware‑level awareness of DMA engines, multi‑level memory hierarchies, and complex number handling in MLIR. Why This Role Is Different This isn’t a “make the existing thing faster” role. There is no existing compiler; you will be writing the compiler that a brand‑new class of 5G/6G AI silicon runs on. Your decisions at the IR level will directly shape what that hardware can and cannot do for the next generation of telecommunications infrastructure. If you want to work on a problem where the compiler, the hardware, and the research are all moving simultaneously—and where your code will eventually run at the edge of the global wireless network—this is the right opportunity. Application Process We use a merit‑based hiring approach that values diverse experiences, perspectives, and skillsets. Ericsson is proud to be an Equal Opportunity employer. Benefits and Compensation Competitive salary based on location and experience. Comprehensive health benefits, 401(k) with employer match, paid vacation, sick leave, maternity leave, and additional company‑paid benefits such as financial wellness programs and educational assistance. Equal Opportunity Statement Ericsson is proud to be an Equal Opportunity employer. To request accommodations due to a disability, contact Ericsson at View email address on click.appcast.io. #J-18808-Ljbffr Ericsson GmbH