Hardware Design Engineer

We are seeking a highly skilled ASIC Design / SDC Engineer to join a world-class silicon engineering team building next-generation networking chips for high-performance, web-scale, and service provider systems. The ideal candidate is a detail-oriented engineer who enjoys solving deep timing and constraint challenges, collaborating across disciplines, and driving silicon-level correctness from block to full chip. What You Will Do Develop and maintain block-level and full-chip SDC constraints across functional and test modes Drive timing closure in collaboration with RTL, physical design, and DFT teams Define and validate constraints using industry-standard STA and constraint verification tools Analyze and resolve timing issues across complex multi-clock, multi-mode designs Work with architecture teams to understand clocking structures and timing intent Review and improve SDC quality, completeness, and correctness across blocks and full chip Improve methodologies for SDC reuse, propagation, and constraint automation Support full-chip clocking strategy, diagrams, and documentation Optionally contribute to RTL design or IP integration What You Bring 4–6+ years (Master’s) or 6+ years (Bachelor’s) of ASIC / digital design experience Strong expertise in SDC development and static timing analysis (STA) Deep understanding of clock domains and clock gating Deep understanding of timing exceptions including false paths and multi-cycle paths Deep understanding of asynchronous boundary handling Experience with tools such as Synopsys Design Compiler, DCG, or Fusion Compiler Experience with tools such as PrimeTime or equivalent STA tools Strong Verilog / SystemVerilog knowledge Proficiency in scripting languages, especially Tcl (required), Shell, and Perl (preferred) Experience working across block-level and full-chip timing closure Nice to Have Experience with timing constraint verification tools such as TCM or TimeVision Exposure to RTL design or microarchitecture Background in high-performance networking, ASIC, or SoC development Experience improving EDA flows or design methodologies Ideal Candidate The ideal candidate is a detail-oriented engineer who enjoys solving deep timing and constraint challenges, collaborating across disciplines, and driving silicon-level correctness from block to full chip. #J-18808-Ljbffr