Senior ASIC PD Engineer - Cache Coherent Interconnects

NVIDIA Corporation in Santa Clara, CA seeks a CPU Cache Coherent Interconnects Design Engineer to own the physical design of the on-chip interconnect network and last-level caches. You will perform synthesis, timing closure, and power optimization while collaborating with the logic team on micro-architecture feasibility. You will evaluate PD for next-generation Nvidia coherent interconnects and system-level caches, contribute to RTL design/verification, and navigate the ASIC flow with DFT/ECO #J-18808-Ljbffr