Senior Staff Engineer, NPI Packaging R&D

Location San Diego, CA, US Company Overview pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30‑year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world‑class capabilities with high‑performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better. Job Summary We are seeking an experienced Senior Staff Engineer to lead pSemi’s internal prototyping assembly laboratory. The laboratory operates in a very high‑mix low‑volume environment and supports the assembly of R&D prototypes, reliability test samples and engineering samples shipped to customers for testing. The role requires expertise in the assembly processes required for fully packaged, single die flip‑chip LGA, multi‑chip modules (MCM) and System‑in‑Package devices. Assembly processing includes paste / flux screen printing for SMT components, SMT pick‑and‑place, flip‑chip attach, mass re‑flow, underfill dispense, potting or encapsulation via dam & fill, laser marking and package singulation. The ideal candidate will have extensive hands‑on experience with automated semiconductor assembly equipment such as paste / flux printers, SMT pick‑and‑place, plasma clean, underfill / potting compound dispensers, plasma cleaner, laser markers and saw singulation equipment. The candidate should also be knowledgeable of the different semiconductor industry standards based on IPC, JEDEC, MIL spec, EIA and SMTA, as well as expertise in product qualification, process development, and team leadership. In addition, the candidate should be aware of developments in assembly and packaging technologies like WLFO, CoWos, etc. Key Responsibilities Cross‑Functional Leadership: Guide cross‑functional teams in making critical packaging mechanical decisions throughout the product development stages. Process Development & Risk Mitigation: Define and develop manufacturing processes by performing detailed design analysis (tolerance analysis, RMS, FMEA, etc.) and guiding risk assessments. Design Documentation & Oversight: Coordinate preparation of design documentation, BOM, and assembly process flows, ensuring all aspects meet technical specifications and quality standards. Team Mentorship: Mentor junior engineers and lead technical development efforts across packaging and assembly disciplines. Failure Analysis & Problem Resolution: Root cause analysis and resolution of issues during both the development and production phases. Minimum Qualifications (Experience and Skills) Education: Bachelor’s degree in Engineering (Mechanical, Electrical, Packaging, Materials, or Chemical), Physics, or Chemistry. MS preferred. Experience: At least 12 years in electronics packaging, including 5 years of hands‑on experience in the assembly of LGA, MCM and SiP‑specific assembly processes and packaging‑related technologies. Document Management systems: experience working with document management systems, e.g. Agile, the ECO process and Product Life Cycle management. Process Documentation: Ability to document the assembly process flow via standard process descriptions, detailed work instructions, quality specifications based on JEDEC & MIL standards. Design & Development Tools: Proficient with design tools such as AutoCAD, Cadence Allegro, CAM350 or similar. Hands‑on experience with Solidworks for basic 3D model generation. Experience setting up and overseeing operation of a semiconductor proto‑assembly lab for quick‑turn customer sampling. Packaging Knowledge: In‑depth understanding of microelectronic packaging technologies, including flip‑chip bumping, wafer backend processing and SMT. Cross‑Functional Team Leadership: Experience leading cross‑functional teams in a fast‑paced, deadline‑driven environment. Process & Risk Management: Ability to assess design feasibility, conduct cost‑risk analysis and mitigate technical risks during NPI product development. Preferred Qualifications RF Product Design: Experience with the design and packaging of RF products. Statistical Analysis Tools: Familiarity with statistical software or tools for analysis. Automated Task Management: Experience with Excel macros or automation for process optimization, Jira for task management. LGA Package Assembly: Knowledge of the assembly process flow and quality requirements per industry standards. Ability to continuously improve the assembly process flow based on concepts of DfM, DfR and similar. PCB Fabrication: Understanding of PCB fabrication and design processes. Package Reliability & Quality Assurance: Knowledge of semiconductor quality and reliability standards and failure modes. Education Requirements Bachelor’s in Engineering (Packaging, Electrical, Mechanical, Materials or Chemical), Physics or Chemistry; MS preferred. Work Environment This job operates in a professional office environment. This role routinely uses standard office equipment. Physical Demands The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand, walk, use hands to finger, handle or feel and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds. Compensation USD $172,201.96 - $223,874.95 per year EEO Statement pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally‑protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics. Trademarks and Patents Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: #J-18808-Ljbffr