Staff Verification Engineer

Apply advanced verification methodologies to verify memory subsystem designs of the computer systems, including the AMBA5 CHI and AMBA4 AXI bus bridges, the final level caches, the DDRx/LPDDRx memory controllers, and the interfaces with DDR PHY. Interact with design and micro‑architecture teams to review design specifications and understand the functional requirements of the design; execute verification tasks to ensure correctness of functionalities in the design; write functional test plans; build UVM‑based constrained random test benches, including sequencers, generators, drivers, scoreboard, monitors, checkers, and integrate with CHI/AXI verification IPs; write test cases; build Perl/Python scripts to automate the regression tasks; run simulation using Synopsys VCS or Mentor Questa; debug and report failures in the design; collect functional coverage and code coverage; use coverage tools to analyze and tweak tests for coverage; apply assertion‑based verification methodology to facilitate debug; support system integration; build performance test benches on Emulators for silicon bring‑up. Requirements: Master’s degree in Electrical Engineering and four years of experience in design verification, including review specifications, develop attributes, test and coverage plans, define methodology and test benches; work with design and micro‑architecture teams to understand the functional and performance goals of the design; develop and execute block/top level/full chip tests and triage of failures; experiences in the following tools: Python scripting, Verilog/SystemVerilog/UVM; RTL simulation tools (Synopsys, VCS, Mentor Questa); domain knowledge of ONFI, AXI, ACE. #J-18808-Ljbffr FLC Technology Group