ASIC Verification Engineer
$101k - $162kFull-time
Broadcom
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- Develop thorough understanding of IEEE Ethernet protocols.
- Understand chip architecture, microarchitecture and design specification.
- Develop advanced verification environment and testbench components in SystemVerilog UVM.
- Participate in block level and chip level verification tasks.
- Infrastructure work including developing scripts and tools for efficiency and quality improvements.
- Bachelors in Engineering and 5+ years of related experience or Masters degree in Engineering and 3+ years of related experience or PhD and no experience
- Design/Verification experience, or equivalent experience.
- Logic design, Electronic circuit design and related course work to provide a broad background in the area of ASIC design and verification.
- Proficiency with HDL language such as Verilog, SystemVerilog or VHDL is a must.
- Proficiency with C/C++ programming language and hands-on exposure to Object Oriented Programming is a big plus.
- Proficiency with scripting in various languages such as Python, PERL, TCL is a big plus.
- Self-motivated, good communicator, quick learner and good team player.
- Display positive attitude and demonstrate flexibility in day-to-day work.
Vacancy posted 5 hours ago
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