Director, ATE Test Engineering

Join Us At Ampere

Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team.

About The Role

Ampere is seeking a hands-on, high-impact leader to build and scale our ATE Test Engineering organization from NPI through high-volume manufacturing (HVM) of our next-generation power-efficient server products. You will define and execute test strategy, architectures, and operating processes that deliver world-class test coverage, quality, yield, and total cost of test; enabling fast, reliable ramp across multiple product lines.

• Build and scale the organization: Recruit, mentor, and develop a high-performing ATE test engineering team; establish clear technical standards, ways of working, and measurable goals.
• Own end-to-end ATE test strategy: Define ATE test architecture, methodologies, and coverage targets from pre-silicon through HVM, ensuring alignment to product quality and yield requirements.
• Partner cross-functionally: Work closely with Design/DFT, Product/Package, Manufacturing, and Quality to establish testability requirements, DFX-to-test transfer plans, and release criteria.
• Drive NPI execution and production readiness: Ensure robust test bring-up, validation, and production release—meeting targets for cost, schedule, quality, and yield.
• Architect scalable ATE test solutions: Lead the design of flexible, reusable test program structures that enable rapid ramp-up across sites and product variants.
• Oversee high-speed ATE development: Provide technical leadership on high-speed ATE test hardware and interface development for HPC server products (e.g., load-board/probing strategy, instrumentation, timing/accuracy requirements).
• Lead test planning governance: Run and drive alignment in test plan reviews and technical decision forums across engineering, product, and operations.
• Data-driven yield and quality improvement: Analyze yield, scrap, and retest data to identify bottlenecks; drive continuous improvement with product/process teams.
• Lead quality investigations: Own and drive systematic problem solving (e.g., 8D, RCCA) to eliminate root causes and prevent test escapes across products and manufacturing sites.
• Manage external partners and sites: Partner with OSATs/CMs/test houses to ensure process control, rapid excursion response, and strong operational KPIs (e.g., DPPM, yield, escapes, retest rates, throughput).
• Own ATE CAPEX and vendor strategy: Lead budgeting, equipment selection, and sustaining strategies for load boards, probe cards, sockets, instrumentation, and related test infrastructure.
• Establish engineering workflows and rigor: Implement robust software and process practices including version control, code review, CI/CD for test software, change control, golden units, and full traceability.
• Ensure compliance and IP protection: Ensure adherence to applicable standards and robust secure workflows (e.g., ISO 9001; add IATF 16949 / AEC‑Q100 and ISO 13485 if applicable). Protect IP through secure test flows and controlled access.

About You

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field plus 15 years of relevant experience; or Master's degree plus 12 years of relevant experience in semiconductor test engineering, product engineering, or test development.
• 5+ years of leadership experience managing Test and/or Product engineering teams
• Strong expertise in ATE hardware design, test methodology, failure analysis/silicon debug, and test software development (e.g., C/C++, Python)
• Deep knowledge of:
• Scan/ATPG
• Memory BIST
• High-speed I/O testing
• Silicon debug and correlation between test and design behavior
• Proven experience with high-end ATE platforms such as:
• Advantest EXA Scale and/or
• Teradyne UltrFLEX+
• Demonstrated ability to drive alignment across design, product, and operations through influence and data-driven decision-making
• Proven track record managing NPI and scaling into HVM, including global OSAT bring-up and ramp support
• Experience with OSAT/CM operations in Asia, including process control and remote debug; willingness to travel

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $279,500 and $419,500, except in the San Francisco Bay Area where the range is between $293,000 and $440,000. Our benefits include health, wellness, and financial programs that support employees through every stage of life. Benefit highlights include:

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.