Principal ASIC Architect
Dormont Manufacturing Co
About our company - Tensordyne (formerly Recogni) AI is reshaping our world, performing cognitive tasks once unique to humans—perceiving across modalities, learning quickly, and solving complex problems. Tensordyne builds high-performance, low-power generative AI inference systems. We’re leveraging novel techniques from the latest AI research to build custom silicon, hardware, and software to accelerate multimodal generative AI at scale—delivering safe, sustainable, cutting‑edge solutions for hyperscaler and neocloud data centers. Headquartered in Sunnyvale, CA, and Munich, Germany, with remote team members across North America and Europe, Tensordyne is a well‑funded, fast‑moving startup. We support our people with competitive pay, comprehensive benefits, flexibility, and recognition programs—because breakthrough technology starts with a healthy, empowered team. Come join us, as we shape the future of AI together! The Opportunity In this role, you will lead all phases of ASIC architecture definition and design of Tensordyne’s next‑generation family of processors for generative AI inference acceleration. This is an exciting opportunity that involves high‑level silicon architecture planning, hands‑on design, prototyping of ASIC design concepts, mentoring, and technical leadership to deliver the high‑performance multi‑chip silicon solutions that are at the heart of Tensordyne’s vertically integrated, generative AI inference acceleration systems for data centers. What You’ll Do Lead the architectural planning and definition of new Tensordyne AI processors, that consist of highly specialized floating point AI compute cores, embedded memory, embedded RISC‑V CPU cores, and high speed serial communications with chip‑to‑chip networking fabric, HBM, and PCIe connectivity. Analyze technical needs, propose chip design solutions, create detailed design specifications, lead architectural modeling and establish ASIC development milestones to ensure that the final product meets requirements related to functionality, inference performance, inference accuracy, power efficiency, programmability, debuggability and manufacturability. Work closely with external engineering partners, ASIC design engineers, ASIC design verification teams, SOC physical design teams, interdisciplinary software teams, product management and executives, providing technical guidance, overseeing design reviews and mentoring where applicable. Lead the evaluation of new silicon IP technologies, EDA tools and methodologies to enhance the product and improve the efficiency of our chip design process. What You’ll Bring 15+ years of hands‑on experience and deep expertise in silicon design engineering and architectural planning of high performance compute (HPC) processors like GPUs, CPUs, TPUs etc., as well as HBM and high speed SerDes networking technologies for AI workloads. Strong understanding of generative AI algorithms, attention mechanisms, foundation transformer models, and mapping these functions to hardware. Strong Verilog programming skills, and experience with RTL verification, and performance modeling. Experience with performance analysis, debugging, and optimization is also required. Track record of developing architectural C‑models, SystemC, or TLM. Expert‑level skills in C/C++, and scripting languages like Python or Perl for automation and modeling. An MS or PhD in Electrical Engineering, Computer Engineering or related engineering discipline. For this role, occasional travel is needed to interact with global engineering partners. Tensordyne’s culture was built on the following values Put people first. We only succeed when our people succeed. Ethics and integrity always; Being open, honest, and respectful of everyone. Think Big. Be ambitious and have audacious goals. Aim for excellence. Quality and excellence count in everything we do. Own it and get it done. Results matter! Make each person better together, than they would be as an individual. Embrace each others’ differences, and embrace that there will be differences. Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. #J-18808-Ljbffr Dormont Manufacturing Co
$258k - $294k
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Responsibilities Develop innovative high-performance processor and system architectures, focusing on the memory system and energy efficiency. Develop architecture and micro‑architecture features to improve the state‑of‑the‑art in GPU memory systems, optimizing along...Principal- A leading aerospace company is looking for a Principal DFT Engineer in Sunnyvale, CA, to lead the design and optimization of DFT architectures for advanced ASICs. The role involves collaborating with cross-disciplinary teams and ensuring efficient test methodologies for...Principal
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## Principal Power and Thermal Innovation ArchitectApplylocations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition... ...the Silicon Co-Design Group (SCG). We are hiring a Principal Architect to scout the research and industry landscape, identify...Principal$190k - $280k
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...flexibility to accelerate innovation. About the Role The DFT Architect at Altera is a senior technical authority responsible for... ...architecting and implementing DFT solutions for complex SoC, FPGA, ASIC, or multi‑die designs. ~10+ years experience in scan...PrincipalLocal areaShift work$183k - $389.5k
A global edge-to-cloud technology company in Sunnyvale is looking for an experienced Distinguished Technologist, ASIC Design Architect. The role involves owning complex ASIC delivery, defining architecture, and leading engineering teams. Ideal candidates should have 15+...- United States Digital Space LLC in Sunnyvale is seeking a Principal DFT Engineer to lead the development of next-generation ASICs for deployment in space. This role involves implementing and optimizing DFT architectures, ensuring high-performance and reliable connectivity...Principal
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...Principal Architect, AI and Semiconductors, Google Cloud Google San Francisco, CA, USA ; Sunnyvale, CA, USA ~ Bachelor's degree in Computer Science, a related technical field, or equivalent practical experience. ~10 years of experience as an enterprise architect...Principal$239k - $278.75k
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$220k - $250k
...semiconductor startup in Sunnyvale is seeking an RTL Design Tech Lead to oversee micro-architecture and RTL development for complex ASIC/SoC programs. This role requires deep design expertise and technical leadership to guide teams through the architecture and tapeout...
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