Ph.D. Intern - AI/ML, Design Automation

Apply machine learning research to real chip design problems across Marvell's advanced silicon development flow Develop and apply ML models, including graph neural networks, reinforcement learning, and generative approaches, to placement, routing, timing closure, power estimation, and design rule checking Work with production EDA tool flows and real design data from active tapeouts in 3nm and 2nm processes Build predictive models to reduce design iteration cycles and improve first-pass silicon success rates Collaborate with analog, digital, and physical design engineers and validate model outputs against ground-truth silicon results Present research findings and model performance to engineering leadership and contribute to internal technical documentation Design, implement, and evaluate LLM-based tools and agentic workflows for global engineering and operations teams Build RAG pipelines, fine-tuning workflows, and prompt engineering frameworks using Marvell's internal knowledge and tooling ecosystem Evaluate model performance, safety, and reliability in production enterprise environments and iterate based on engineering-team feedback Collaborate with IT, security, and engineering stakeholders on responsible and scalable AI deployment Present implementation results and adoption metrics to cross-functional leadership Requirements Currently enrolled in a Ph.D. program in Computer Science, Electrical Engineering, Data Science, or a related field, with a research focus in machine learning, AI systems, or a related area Hands-on experience building and deploying machine learning systems Applied experience training, evaluating, and deploying ML models using frameworks such as PyTorch or TensorFlow Production-quality Python Familiarity with Git and software development best practices Rigorous experimental methodology and ability to measure results and draw defensible conclusions from data Ability to communicate technical work clearly to research and engineering audiences and present and defend work Track 1: Coursework or research experience in VLSI design, digital or analog circuit design, computer architecture, or EDA Track 1: Familiarity with graph-based ML methods, reinforcement learning, or generative models applied to structured engineering data Track 1: Exposure to EDA tools or chip design flows such as Cadence or Synopsys is a strong plus Track 2: Demonstrated full-stack experience with LLMs, multimodal models, RAG pipelines, and agentic protocols such as MCP and A2A Track 2: Hands-on knowledge of transformers, diffusion models, and orchestration tools such as LangChain, LangGraph, AutoGen, CrewAI, LlamaIndex, or Hugging Face Track 2: Rigorous model benchmarking and evaluation, including identifying failure modes and proposing enhancements Track 2 preferred: Experience with agentic reasoning, planning, and tool-use patterns in multi-agent orchestration frameworks such as n8n or AutoGen Track 2 preferred: Exposure to end-to-end data pipeline development and model deployment with data engineering or platform teams Track 2 preferred: Ability to independently research and implement concepts from current AI literature Applicants must be eligible to access export-controlled information under U.S. export control laws; some applicants may require export license review Core Competencies Demonstrates expertise in machine learning model development and deployment, particularly in the context of chip design and EDA tools. Proficient in Python programming and familiar with frameworks such as PyTorch and TensorFlow, with a strong emphasis on collaboration and communication within cross-functional teams. Highest-signal resume keywords Machine Learning Model Development Python Programming Graph Neural Networks EDA Tool Experience Reinforcement Learning Hard Skills Machine Learning Graph Neural Networks Reinforcement Learning Generative Models Python PyTorch TensorFlow EDA Tools VLSI Design Model Evaluation Soft Skills Communication Collaboration Problem-Solving Research Skills Presentation Skills Industry Keywords Chip Design Silicon Development EDA AI Systems Export Control Laws Tools & Technologies Cadence Synopsys LangChain Hugging Face AutoGen CrewAI LlamaIndex N8n MCP A2A #J-18808-Ljbffr Jobtailor