Senior ASIC Timing & Closure Engineer
NVIDIA Gruppe
NVIDIA Gruppe is seeking a talented engineer to lead timing analysis and closure for advanced GPUs and CPUs. You will collaborate with cross-functional teams to devise timing closure strategies and will leverage your expertise to enhance our innovative projects. The ideal candidate possesses a BS in Electrical or Computer Engineering with 5 years of relevant experience, including strong skills in Static Timing Analysis and timing closure processes. Excellent benefits and equity opportunities await. #J-18808-Ljbffr
- ...seeking a candidate in Santa Clara for a role focusing on timing analysis and closure for DFT logic across its chips, including GPUs, CPUs, and... ...of 5 years of experience in Electrical or Computer Engineering. You will collaborate across teams to drive timing constraints...Senior
$136k - $218.5k
...Responsibilities Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block... ...BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience...Senior$136k - $218.5k
...lasting impact on the world. What you’ll be doing: Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA... ...BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience)...Senior- A leading technology company is seeking a Cellular ASIC Design Engineer to develop and optimize the design and methodology for integrated... ...a strong VLSI background, with responsibilities including timing closure, power optimization, and collaboration with cross-functional...Senior
$136k - $218.5k
...and accelerated computing, we seek a Senior LPU ASIC Engineer to contribute to our outstanding progress... ..., floorplanning, place & route, timing constraints, UPF and LEC at the block/... ...implementation. Tapeout Execution: Lead design closure in collaboration with IP, PnR, Sign-...SeniorFull time$168k - $264.5k
...circuits team alongside custom circuit designers to drive timing analysis and closure of custom circuit macros (digital, semi-custom and mixed-... ...BS (or equivalent experience) in Electrical or Computer Engineering 6+ years of experience for Masters and 8+ years for Bachelors...Senior$168k - $264.5k
...lasting impact on the world. We are now looking for a motivated Senior Timing Engineer (Circuits) to join our dynamic and growing Circuit... ...modes e.g., shift, capture, BIST, etc. Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs...SeniorShift work$120k - $220k
...quality of life. We are seeking a Senior STA Methodology Engineer to join our ASIC design team. In this role, you will own cross-functional timing methodology efforts across multiple IPs... ...production STA flows, drive signoff closure, and introduce data-driven techniques...SeniorFull timeWork at officeImmediate startVisa sponsorshipNight shift$126.8k - $220.9k
...A leading technology company seeks an ASIC STA Engineer to manage SoC design timing. Responsibilities include timing sign-off and collaborating across teams for timing closure. Ideal candidates should have a Bachelor's in Electrical Engineering and 2+ years in ASIC timing...- ...SpaceX is seeking a motivated Sr. ASIC DFT Engineer for their team in Sunnyvale, California. The engineer will work on developing next-generation ASICs for deployment in space and ground infrastructures. Responsibilities include optimizing DFT architectures and collaborating...Senior
- ...L&T Technology Services Limited is seeking an experienced engineer with over 5 years of hands-on expertise in DFT and ATPG for SoC or ASIC designs. The candidate should have a strong understanding of DFT fundamentals, including controllability, observability, and scan...Senior
- ...NVIDIA Gruppe is looking for a skilled engineer to join their TensorRT Edge-LLM team in Santa Clara, California. The role involves developing... ...framework for large language models and optimizing it for real-time performance on embedded platforms. Candidates should have a...Senior
$142.2k - $213.4k
A leading tech company is seeking a DFT Engineer to work closely with chip architects and designers on mixed signal and digital VLSI designs... .... Ideal candidates will have extensive experience in digital ASIC design, proficiency in Verilog or VHDL, and expertise with Mentor...Senior- NVIDIA Gruppe in Santa Clara is looking for a motivated Senior Timing Engineer (Circuits) to join its Circuit Solutions Group. The candidate will work on timing analysis and signoff for innovative processor designs. Ideal candidates should have over 6 years of experience...Senior
$141.3k - $226k
...and gate simulations and work with design engineers to verify fixes. Write diagnostics for... ...validation of FPGA prototypes (pre‑tapeout) and ASIC. Replicate silicon bugs in simulation... ...holidays, paid sick leave and vacation time. The company follows all applicable laws...SeniorLocal area- A pioneering technology firm in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to ensure the functional correctness of high-speed low-power digital integrated circuits. The ideal candidate will have significant experience in ASIC verification, particularly...Senior
- ...their team in Santa Clara, California. The ideal candidate will have over 5 years of hands-on experience in DFT and ATPG for SoC or ASIC designs, coupled with strong analytical and problem-solving skills. Responsibilities include working on cutting-edge semiconductor programs...Senior
$150k - $220k
E-Space in Saratoga is seeking a Senior ASIC Design Engineer to join our processor subsystem team. This full-time role focuses on the configuration, integration, and verification of Arm processor IP for satellite IoT connectivity ASICs. You will collaborate with SoC architects...SeniorFull time- SpaceX is seeking a Sr. ASIC DFT Engineer to develop advanced ASICs for space and ground infrastructures. This role involves optimizing DFT architectures and collaborating with various engineering teams to enhance the Starlink network's capabilities. Ideal candidates will...Senior
- ...NVIDIA Gruppe in Santa Clara is seeking a Timing Methodology Engineer to optimize performance and reliability across their product portfolio, including consumer graphics and AI applications. The role involves improving sign‑off strategies, collaborating with technology...Senior
$225k
...Frey Consulting Group is seeking 4 experienced ASIC/VLSI Engineers for permanent, full-time, onsite roles in Silicon Valley. The successful candidates will support advanced semiconductor and AI/networking programs with tier-1 clients. Key requirements include 8+ years...SeniorPermanent employmentFull time$135k - $160k
...with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience... ..., diagnosis, and hierarchical test flows. Run and debug non‑timing and SDF annotated gate‑level simulations. Create and...SeniorPermanent employmentTemporary workWorldwideWeekend work$159.7k - $230k
...Drive new product introduction (NPI) from engineering builds through production release,... ...optimization, process simplification, and cycle time improvements. Track supplier performance... ...engagement. Preferred Qualifications FPGA, ASIC, or SoC backend experience, particularly...SeniorHourly payContract workPart timeLocal areaShift work$136k - $218.5k
...Senior ASIC Power Engineer We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our next‑generation mobile, embedded, and datacenter platforms. This position offers the opportunity...Senior- A leading technology company based in Santa Clara, California is looking for an experienced ASIC Design Engineer to join their Integrated Wireless Technology team. As a key contributor, you will develop micro-architecture specifications and design low-power solutions within...Senior
$116k - $189.75k
...NVIDIA Corporation in Santa Clara is seeking an ASIC Clocks Verification Engineer to collaborate with ASIC designers and verification engineers. You will verify high-frequency clock structures and design GPU clock architecture to meet requirements. The ideal candidate...Senior$153.2k - $229.8k
A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree...Senior- ...NVIDIA Corporation is hiring a Senior ASIC Verification Engineer in Santa Clara, California. This position involves verifying designs and implementations of cutting-edge SoCs and GPUs, along with defining verification strategies and collaborating with ASIC designers. Candidates...Senior
$112.2k - $242k
...company in Mountain View is seeking a Design Verification Engineer to architect verification environments for ASIC SoCs. The ideal candidate will have a minimum of 8... ...on skills and experience. This role is full-time with opportunities for career growth. #J-18808-Ljbffr...SeniorFull time$168k - $264.5k
...system connecting multiple ASIC chips together and FPGA... ...hardworking systems engineers who will craft FPGA... ...are now looking for a Senior Systems Prototyping Engineer... ...the prototype, analyze timing and generate bit... ...Synthesis, P&R and Timing closure, with emphasis on Synopsys...Senior
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