Senior FPGA Engineer

To drive the architecture of cutting-edge Communications Test & Measurement products, the remote Senior FPGA Engineer will own FPGA design, manage timing closure strategies, and mentor team members while addressing complex technical challenges. Key responsibilities Define and drive end-to-end FPGA architecture, including make/buy tradeoffs and timing closure strategies for multi-gigabit designs Serve as the final technical escalation point for FPGA design and debug issues, mentoring other engineers in the process Lead root-cause analysis of silicon and board bring-up issues that require advanced troubleshooting Required qualifications BS or MS degree in Electrical and/or Computer Engineering with 12-15 years of relevant experience, including 5+ years in architecting multi-Gbps SerDes/transceiver-based FPGA designs Demonstrated expertise in high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL Deep hands-on experience with FPGA transceivers, hard IP, and PLLs, including timing closure and link debug at multi-Gbps rates Proven track record of closing timing and debugging link-layer issues on high-speed Ethernet and IP protocol stacks in production designs Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains