DFT Design Engineer - SoC/ASIC Test & MBIST Expert
Cadence
Cadence in Austin, Texas is searching for an SoC/ASIC Digital Design Engineer with a focus on Design for Test (DFT). Candidates should possess 2-10 years of experience, along with expertise in scan chain insertion and automatic test pattern generation (ATPG). This position requires a self-driven individual with strong problem-solving skills who can work effectively in a collaborative team environment. US citizenship is required to apply. #J-18808-Ljbffr Cadence
Vacancy posted 5 days ago
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