Senior Signal Integrity / Power Integrity (SI/PI) Engineer

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges.

At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.

Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.

We are growing in Roseville! Be among the founding engineers shaping Arista’s new Roseville R&D Lab where you’ll help design next-generation networking technology alongside some of the industry’s brightest engineers.

Who You'll Work With

Arista’s cutting-edge Ethernet and optical networking platforms are built to push the limits of performance, density, and power efficiency. This wouldn’t be possible without our Signal Integrity (SI) and Power Integrity (PI) engineers who design, simulate, and characterize interconnects enabling the fastest SerDes technologies in the industry. We’re looking for a Senior Signal Integrity / Power Integrity Hardware Engineer to join our Hardware Design team at our headquarters in Santa Clara, CA. In this role, you’ll work at the intersection of advanced simulation, next-generation SerDes (112G/224G/448G PAM4), and innovative routing, packaging, and power delivery techniques. Your work will directly influence the architecture and layout of Arista’s next-generation Ethernet and optical systems for hyperscale, AI, and cloud networking.

The total estimated annual compensation range for this position, inclusive of base salary, bonus, and equity, is $260,000 to $470,000. This range is a good faith estimate only. Bonus and equity are discretionary, subject to plan terms, and are not guaranteed components of total compensation. Actual total annual compensation may vary based on employee performance, company or equity performance, company policy, board approval, or similar factors. Please see additional base salary information below.

What You'll Do

• Perform 3D EM design and simulation of high-speed interconnects (channels, vias, packages, and connectors) for 112G/224G PAM4 SerDes using tools such as Ansys HFSS, SiWave, and Cadence Sigrity.
• Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.
• Conduct S-parameter and time-domain measurements (VNA, TDR, BERT) to extract channel performance and validate modeling correlation.
• Perform link-level analysis for advanced standards (Ethernet 800G/1.6T, PCIe Gen6/Gen7, CXL) using tools such as Keysight ADS or Cadence SystemSI.
• Collaborate closely with hardware, mechanical, and packaging teams to optimize stack- up, breakout, and routing strategies for high-density designs.
• Research and prototype novel materials, backplane concepts, and low-loss interconnect topologies to meet next-generation performance targets.
• Support bring-up and debug of production boards, working cross-functionally to root-cause SI/PI issues.

• BS/MS/PhD in Electrical Engineering, Physics, or related field with a focus on electromagnetics, signal integrity, or high-speed digital design.
• Solid understanding of signal integrity theory, S-parameter analysis, and channel modeling.
• Hands-on experience with 2.5D/3D EM solvers (Ansys HFSS, SiWave, Sigrity, CST).
• Strong lab skills using oscilloscopes, VNAs, TDRs, BERTs, and Ethernet compliance tools.
• Familiarity with advanced PCB materials (e.g., Megtron 7, Tachyon 100G, SLP) and manufacturing constraints for high-speed design.
• Experience analyzing and simulating 56G/112G/224G PAM4 and NRZ serial links.
• Knowledge of power integrity and co-simulation techniques is a plus.
• Excellent communication and collaboration skills.

Preferred Qualifications

• Experience with co-packaged optics, chiplet-based architectures, or advanced substrate technologies.
• Familiarity with EMI/EMC considerations and signal/power isolation in densely integrated photonic-electronic systems.
• Understanding of thermal and mechanical effects on SI/PI performance and long-term reliability.
• Experience working with fabrication vendors, ASIC teams, and contract manufacturers to ensure end-to-end channel integrity.

Base Salary Information:

The new hire base pay for this role has a pay range of $162,000 to $225,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The salary range provided reflects base pay only. As described above, this position may also be eligible for discretionary Arista bonuses and equity. US- based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

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Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.