Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

STA CAD Engineer — Gate-Level Timing & Flows

Apple Inc.

A leading technology company in San Jose, California, is seeking an experienced CAD Engineer to develop and maintain gate-level STA flows for Silicon designs. This role involves working closely with design teams, improving performance methodologies, and utilizing advanced programming skills, particularly in Python and Tcl. Candidates must have at least 10 years of industry experience and a relevant bachelor's degree. The position offers a competitive salary range and comprehensive benefits, including stock options and educational reimbursement. #J-18808-Ljbffr Apple Inc.

Vacancy posted 4 days ago
Similar jobs that could be interesting for youBased on the STA CAD Engineer — Gate-Level Timing & Flows in San Jose, CA vacancy
  • A leading tech company in San Jose is seeking a CAD Engineer focused on timing methodologies for gate-level flows. In this role, you will develop and enhance STA flows, collaborate with design teams on timing issues, and support methodologies for timing verification. Ideal... 
    Suggested

    Apple Inc.

    San Jose, CA
    4 days ago
  • $147.4k - $272.1k

    CAD Engineer - Timing for Gate-Level Flows & Methodologies Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see...  ...love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to... 
    Suggested
    Relocation

    Apple Inc.

    San Jose, CA
    5 days ago
  • $181.1k - $318.4k

    CAD Engineer - Timing for Gate-Level Flows & Methodologies Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see...  ...love with their devices! Description As a member of our STA CAD team, you will: Develop, maintain, and enhance existing... 
    Suggested
    Relocation

    Apple Inc.

    San Jose, CA
    3 days ago
  • A leading tech company in San Jose is seeking a CAD Engineer to develop and enhance gate-level STA flows for silicon designs. The ideal candidate has 10+ years...  ...You will collaborate with design teams to analyze timing-related issues and improve overall STA methodology.... 
    Suggested

    Apple Inc.

    San Jose, CA
    5 days ago
  • $147.4k - $272.1k

     ...member of our best‑in‑class CAD Group, you will be part of developing...  .../power grid extraction, STA timing, signal/power EM analysis,...  ...various IR/EM analysis and signoff flows. Supporting and...  ...flow. Experience in electrical engineering machine learning applications... 
    Suggested
    Relocation

    Apple Inc.

    Sunnyvale, CA
    1 day ago
  • $147.4k - $272.1k

     ...member of our best-in-class CAD Group, you will be part of building...  ...the methodologies and flows for gate-level, as well as transistor level...  ...of the world\'s leading engineers, and help us deliver the next...  ...involved in EMIR - extraction, timing, noise, simulation, physical... 
    Relocation

    Apple Inc.

    Sunnyvale, CA
    4 days ago
  • $127.4k - $184.4k

     ...About the Role ML/AI Timing and Power Flow Expert - a highly skilled...  ...full‑chip and block‑level designs. You will leverage...  ..., physical design, CAD, library, and...  ...lifecycle. Own and drive STA flows, including timing...  ...strong coding and software engineering practices. Apply ML/... 
    Local area
    Shift work

    Altera

    San Jose, CA
    1 day ago
  • $147.4k - $272.1k

    A major tech corporation in Sunnyvale is looking for an EMIR CAD Engineer to innovate and enhance EM/IR design methodologies. This role involves developing solutions for accuracy challenges and collaborating with design groups. The position offers a competitive salary... 

    Apple Inc.

    Sunnyvale, CA
    4 days ago
  • $88.8k - $187.74k

     ...evolve Mixed Signal-ASIC CAD and EDA methodologies...  ...teams to improve tools, flows, and signoff practices...  ...quality, performance, and time‑to‑market. Your Role &...  ...at block and chip level Interpret and resolve...  ...work effectively across engineering disciplines and influence... 
    Full time
    Local area

    Capgemini Engineering

    San Jose, CA
    4 days ago
  • $88.8k - $187.74k

    Capgemini is seeking an ASIC CAD/EDA Flow/Methodology Developer in San Francisco to innovate on complex design methodologies. The role requires...  ..., with a comprehensive benefits package including medical coverage, retirement plans, and paid time off. #J-18808-Ljbffr Capgemini

    Capgemini

    Santa Clara, CA
    5 days ago
  • $120k - $220k

     ...are seeking a Senior STA Methodology Engineer to join our ASIC design...  ...own cross-functional timing methodology efforts across...  ...production STA flows, drive signoff closure...  ...and maintain scalable CAD utilities and STA flow...  ...implications (DVFS, power gating) • Exposure to interface... 
    Full time
    Work at office
    Immediate start
    Visa sponsorship
    Night shift

    E-Space

    Saratoga, CA
    20 days ago
  • $181.1k - $318.4k

    CAD Engineer, Silicon Learning and Static Timing Analysis Santa Clara, California, United States Hardware Do you love tackling highly complex challenges with...  ...learnings back into static timing analysis tools, flows, margins, and design closure methodologies to drive continuous... 
    Relocation

    Apple Inc.

    Santa Clara, CA
    3 days ago
  •  ...automation (EDA) and static timing analysis (STA). Combining deep domain knowledge...  ...you to analyze system‑level tradeoffs, balancing accuracy...  ...for mission‑critical sign‑off flows. You are a collaborative...  ...guide both senior and junior engineers, and for your skill in articulating... 
    Temporary work

    Synopsys, Inc.

    Sunnyvale, CA
    2 days ago
  • $100 - $120 per hour

    Job Title CAD/PDK Engineer Position Description Protingent Staffing has an...  ...nodes (Foundry 4nm, 2nm etc.) Flow set up and design environment...  ...D for BEOL, VIAs, transistor level as well as Cell level flows....  ...-tax commuter benefits, Paid Time Off (PTO), and an... 
    Contract work
    Work experience placement

    Protingent

    San Jose, CA
    1 day ago
  • $90 - $95 per hour

    Job Title CAD Engineer Position Description Protingent Staffing has an exciting...  ...maintain, and enhance EDA/CAD flows for ASIC design (RTL GDSII...  ...teams (RTL, PD, DV, DFT, STA) to identify gaps and implement...  ...data formats (logs, reports, timing/power data, etc.) Experience... 
    Contract work

    Protingent

    San Jose, CA
    3 days ago
  • $90 - $95 per hour

    Position: CAD Engineer (San Jose, CA) Job Overview: We are seeking a highly...  ...and enhance ASIC design flows across the full development lifecycle...  ..., Design Verification, DFT, STA) to identify gaps and...  ...including logs, reports, and timing/power data Experience using AI... 
    Hourly pay
    Contract work
    Monday to Friday
    Day shift

    Saigepartners

    San Jose, CA
    4 days ago
  • $181.1k - $318.4k

     ...supporting the implementation flow from RTL through GDS signoff. You...  ...through place‑and‑route and timing signoff to show actual PPA improvements...  ...implementation flows (PNR, STA, power analysis) Apply...  ...Genus Experience working with CAD tools & flow Minimum requirement... 
    Relocation

    Apple Inc.

    Cupertino, CA
    3 days ago
  • $147.4k - $272.1k

     ...among place and route engineers, set goals and...  ...domains like top, STA, block place and route...  ...Resolve design and flow issues related to physical...  ...design, budgeting, timing and physical...  ...SoC designs (>20M gates) with frequencies in...  ...is required. From a CAD tool perspective,... 
    Temporary work
    Relocation

    Apple Inc.

    San Jose, CA
    1 day ago
  • $168k - $264.5k

    NVIDIA Corporation is looking for a VLSI CAD Engineer in Santa Clara, California. You will join a team innovating in custom RAM design, requiring skills in CAD flow development and strong programming capabilities in languages like Bash, TCL, and Python. This role involves... 

    NVIDIA Corporation

    Santa Clara, CA
    4 days ago
  • Experis is seeking an ASIC CAD/EDA Flow/Methodology Developer in San Jose, California. Join their Engineering Department to support design and development teams while working on cutting-edge technology. Qualifications include 8+ years of experience in analog/mixed-signal... 

    Experis

    San Jose, CA
    1 day ago
  •  ...Clara, California, is seeking a Staff Hardware Engineer for their Hardware Engineering group. The role involves maintaining CAD infrastructure and ensuring integration of...  ...experience with physical design verification flows, excellent knowledge in Python and scripting... 

    Achronix Semiconductor Corporation

    Santa Clara, CA
    3 days ago
  • $126.8k - $220.9k

     ...Description As an ASIC STA Engineer, you will have responsibilities...  ...SoC design in terms of timing. Key responsibilities...  ...-off, STA and sign-off flow development, ownership of IP and block level timing constraints both...  ...and clock structure, with CAD to understand and... 
    Relocation

    Apple Inc.

    Cupertino, CA
    3 days ago
  • $100 - $120 per hour

    Position: Senior CAD Engineer (San Jose, CA) Job Overview We are seeking...  ...responsible for PDK enablement, CAD flow development, and layout...  ...EMX and Quantus Support top‑level layout and sub‑cell development...  ...including planar, FD‑SOI, FinFET, and Gate‑All‑Around (GAA). Strong... 
    Hourly pay
    Contract work
    Monday to Friday
    Day shift

    Saigepartners

    San Jose, CA
    4 days ago
  • $136k - $218.5k

    NVIDIA is looking for a CAD Engineer to join our SOC Design Methodology...  ...refine, and maintain system-level methodologies and software tools...  ...top-level assembly tools and flows written in C++. Design,...  ...synthesis, place and route, timing/quality checks) is a plus. Excellent... 

    NVIDIA

    Santa Clara, CA
    3 days ago
  •  ...company in Santa Clara is seeking a Physical Design Methodology CAD Engineer to tackle key design challenges in next-generation processors....  ...Ideal candidates will have a BS plus 10 years of experience in CAD flow and proficiency in Tcl, Python, or Perl scripting. This role... 

    Apple Inc.

    Santa Clara, CA
    1 day ago
  •  ...company located in San Jose is seeking a Physical Design Methodology CAD Engineer. In this role, you'll tackle physical design challenges and...  ...in Tcl, Python, or Perl, and has hands-on knowledge of CAD flow development. The role offers a competitive salary range and comprehensive... 

    Apple Inc.

    San Jose, CA
    4 days ago
  • $126.8k - $190.9k

     ...leading technology company is seeking a Physical Design Methodology CAD Engineer in San Jose, California. This role involves developing...  ...collaborating with cross-functional teams, and supporting implementation flows for various projects. Candidates should have knowledge of... 

    Apple Inc.

    San Jose, CA
    4 days ago
  • $100k

     ...Clara, CA Job Type: Full-Time Company: Upscale AI...  ...strategies to enhance engineering efficiency Create and...  ...documentation for tool usage, flow methodologies, and best...  ...and supporting CAD infrastructure for ASIC...  ...Upscale AI’s internal leveling guidelines and benchmarks... 
    Full time

    Upscaleai

    Santa Clara, CA
    5 days ago
  • $138k - $198k

     ...PhD degree in Electrical Engineering, Computer Engineering,...  ...Ability to start full-time role in 2026. About The...  ...systems. As a Silicon CAD Engineer, you will...  ...design tools and design flows that speed the development...  ...are determined by role, level, and location. Within... 
    Full time
    Immediate start
    Worldwide

    Google

    Sunnyvale, CA
    3 days ago
  • $126.5k - $234.9k

     ...seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team...  ...be working on CAD tool, flow and methodology development...  ...throughput, minimize turnaround time (TAT), and improve overall...  ...utilities and infrastructure‑level automation. Working... 
    Work at office
    Remote work
    Flexible hours
    3 days per week

    Rambus.com

    San Jose, CA
    3 days ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to STA CAD Engineer — Gate-Level Timing & Flows. Be the first to apply!