Senior Mixed-Signal RTL Design Engineer
Intel Corporation
Intel Corporation's Central Engineering Group seeks an experienced RTL designer to develop logic for mixed-signal IPs, including cell libraries and IP blocks, ensuring robust verification and clean integration into SoCs. You will collaborate across analog, digital, and physical design teams throughout the design cycle. The role emphasizes ownership of subsystems end-to-end, extensive Verilog/SystemVerilog expertise, and strong debugging skills to meet strict power, timing, and area goals. #J-18808-Ljbffr Intel Corporation
Vacancy posted 15 hours ago
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