SerDes Circuit Design Engineer

Cupertino, California, United States Hardware We are seeking talented Analog Mixed‑Signal designers to join our high‑speed SerDes team. Our team specializes in building next generation high‑performance wireline transceivers delivering intellectual‑property (IP) for Apple’s world‑leading system‑on‑chip (SOC). In this role, you will actively work with cross‑functional Analog Mixed‑Signal design teams to create, execute and drive state‑of‑the‑art IPs key to Apple’s products. You will be challenged to make the best‑in‑class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs that make the best systems. This enables you to learn end‑to‑end system while exceeding the highest expectations of quality, innovation and efficiency. If you have strong fundamentals and a track record of tackling technical challenges, if you are passionate about learning new skills and improving the value of your work, if you like to be tuned to the big picture while diving deeply into the details to innovate and tackle problems, we invite you to join and grow with our team! Description You will work on the development of high‑performance and high‑speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high‑speed clock generation and low‑jitter distribution, phase interpolator, DLL, VCO, LDO) with best‑in‑class power, performance, and area (PPA). You will be leading discussions with cross‑functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block‑level specifications, mixed‑signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on a regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth‑oriented work environment. Minimum Qualifications BS and a minimum of 10 years relevant industry experience. Preferred Qualifications Deep understanding of analog mixed‑signal design with experience in high‑speed serial links. Experience designing analog mixed‑signal circuit blocks including bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched‑cap circuits, ADCs, DACs, oscillators, filters. Understanding of analog mixed‑signal concepts like mismatch mitigation, linearity, stability, low‑power and low‑noise techniques. Understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops). Proven track record of working with system and architecture teams to drive block‑level and IP requirements for high‑speed IO in 100+ Gbps NRZ and PAM applications. Proven track record of working with large teams and guiding junior engineers to develop circuit components required in TX, RX, PLL etc. of a high‑speed IO. Experience with high‑speed digital circuits (e.g., serializer, deserializer, counters, dividers) with solid understanding of digital design concepts. Experience and solid understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de‑emphasis) for 100+ Gbps NRZ and PAM applications. Experience with EQ adaptation methods and circuit implementations to improve PPA. Solid understanding of CDR architectures and implementations. Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS). Hands‑on experience to drive lab testing, debug and data analysis. Hands‑on experience in advanced CMOS technologies, design with FinFet technology. Hands‑on experience with AMS IC development from definition to high‑volume production including layout supervision, bench evaluation, correlation, and characterization. Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime). Concepts of IP delivery and quality checks. Knowledge of common high‑speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired. Skills in scripting and automation to enhance efficiency are highly desirable. Base pay range: $181,100 – $318,400. Your base pay will depend on your skills, qualifications, experience, and location. Apple employees may also participate in discretionary employee stock purchase plans and receive restricted stock units; can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. The role may be eligible for discretionary bonuses, commission payments, and relocation assistance. Benefits include comprehensive medical and dental coverage, retirement benefits, discounted products and services, and tuition reimbursement for formal education related to advancing your career at Apple. Learn more about Apple Benefits. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong. Learn about accessibility in Apple’s workplace. Learn about reasonable accommodations for job applicants. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr Apple Inc.