Power Management Engineer for High‑Performance RISC‑V SoCs

SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to pioneer PMU, clocking and power strategies for high-performance RISC-V CPU and SoC IP. You will work on highly-configurable hardware generators, collaborating with architecture, verification, and software teams to deliver fast, reliable hardware. The role involves microarchitecture development, sandbox verification, and close coordination with physical design to hit frequency and power targets, enabling #J-18808-Ljbffr SiFive, Inc.