Physical Design Flow Engineer
$100kTenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for seasoned Physical Design Flow Engineers to develop implementation flows and methodologies for high-performance, low-power designs on advanced technology nodes, with focus on improving Power, Performance, and Area (PPA) in taped-out designs for its next gen products. This role is hybrid, based out of Santa Clara, CA, Fort Collins, CO or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a BS/MS in Electrical or Computer Engineering, or equivalent experience, with 5+ years in Physical Design and CAD methodology development. You have a strong track record of building implementation flows for high-performance, low-power designs on advanced nodes and delivering measurable PPA improvements in silicon. You are hands-on with industry-standard EDA tools such as Fusion Compiler across synthesis, place-and-route, static timing analysis, and signoff closure. You are proficient in hierarchical design flows, physical design verification, and scripting in Tcl, Python, or Perl to improve automation, robustness, and efficiency. What We Need Lead and contribute to cross-functional efforts that solve complex physical design challenges across multiple IPs, projects, and technology nodes. Develop and maintain RTL-to-GDS methodologies covering floorplanning, synthesis, place-and-route, static timing analysis, signoff, and chip assembly. Optimize EDA tools, flows, and custom CAD solutions to improve PPA, runtime, automation, and overall engineering productivity. Partner closely with physical verification, RC extraction, timing, and DFT teams while driving innovative ML-based approaches to design optimization. What You Will Learn How advanced AI and high-performance silicon products across multiple IPs and nodes shape physical design methodology choices. How to architect and scale end-to-end RTL-to-GDS flows while balancing PPA, runtime, and schedule in a fast-moving environment. Best practices for integrating implementation, signoff, PV/EMIR, RC extraction, STA, and DFT into a unified, high-yield methodology. How to apply data-driven and ML-based techniques to flow optimization and influence EDA vendor roadmaps based on real production needs. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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- ...JD: Job Overview: We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs... ...responsible for various aspects of the backend VLSI design flow, including floor planning, placement, clock tree synthesis (...Suggested
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Apple Inc. in Santa Clara, California is seeking a Physical Design Engineer to join their Digital Design Engineering group. In this role, you will... ...experience in relevant fields, with knowledge of RTL2GDSII flows being a significant plus. Apple offers a competitive salary...$181.1k - $318.4k
...Technologies group, you’ll help design and manufacture our next-... ...requires a mix of strategic engineering along with hands‑on, technical... ...have hands on experience in physical design and large chip integration... ...Floorplanning tools, P&R flows (Cadence or Synopsys) Preferred...Relocation$181.1k - $318.4k
...Technologies group, you’ll help design and manufacture our next-... ...requires a mix of strategic engineering along with hands-on, technical... ...have hands on experience in physical design and large chip integration... ...Floorplanning tools, P&R flows, and global timing verification...Relocation$147.4k - $272.1k
...Technologies group, you’ll help design and manufacture our next-... ...requires a mix of strategic engineering along with hands‑on, technical... ...have hands‑on experience in physical design and large chip integration... ...floorplanning tools, P&R flows, global timing verification and...Relocation$181.1k - $318.4k
CPU Physical Design Methodology and Optimization Engineer Santa Clara, California, United States Hardware Imagine what you could do here. At Apple, new ideas... ...Work with CPU, CAD, and design teams to engineer new flows/algorithms to improve PPA Detailed analysis across...Relocation$181.1k - $318.4k
...groundbreaking Apple products!Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level physical design. Description As a CPU Physical Design... ...design delivery along with closure of backend flows, electrical requirements and improving...Relocation$136k - $218.5k
## Senior Physical Design EngineerApplylocations: US, CA, Santa Claratime type: Full timeposted... ...for a motivated Physical Design Engineer to join our dynamic and growing team. If... ...Ability to form methodologies and automate flows.* Scan insertion and DFT knowledge is a...$181.1k - $318.4k
Physical Design Engineer, Machine Learning You will be part of a hands‑on development team that sets the standard in cultivating excellence, creativity... ...problems. Your work will directly impact vast areas of the flow including RTL design, logic synthesis, floor planning, power...Relocation package$143.1k - $264.2k
SoC Physical Design Engineer, PnR job at Apple Inc.. Sunnyvale, CA. Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary... ...closure for the partitions. Resolve and improve design and flow issues related to physical design, identify potential...Relocation$256.05k - $361.48k
# **Welcome!**## .Senior Physical Design Integration Engineer page is loaded## Senior Physical Design Integration Engineerlocations: US, California, Folsom... ....Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis...Work experience placementLocal areaImmediate startFlexible hoursShift work- ...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...delivery schedules in an ASIC design environment. Experience in design... ...within the RTL-to-netlist flow and collateral handoff processes... ...'s AI/ML infrastructure. Our physical design team transforms RTL...Remote workWorldwide
- ...We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at... ...optimization Identify and address timing bottlenecks early in the flow to improve convergence Preferred Qualifications: Proven...For contractors
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Physical Design Methodology CAD Engineer Santa Clara, California, United States Hardware Do you love creating elegant solutions to highly complex challenges... ...GPU, Analog/Mixed Signal and SOC designs by developing flows, tools and methodologies for future Apple products! You...Relocation$170k - $230k
...ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience... ...RTL/design tradeoffs Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution...Permanent employmentFull timeTemporary workWorldwideWeekend work$200k - $220k
Staff / Senior Staff Physical Design Engineer Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient... ...tapeouts. What you'll do: Ownend-to-end physical design flow: synthesis support, floorplanning, placement, CTS, routing,...- ...Job Title: Senior Physical Design Engineer (MULTIPLE OPENINGS) Salary Range : $216,091-218,000/ Year / 40HRS/WK Location: Cupertino... ...using TCL, Perl, and Python to improve physical design flow efficiency and reduce manual effort. Job Requirements:...
- A leading technology company in California seeks a seasoned Physical Design Engineer to lead projects in advanced semiconductor technology. The ideal... ...will have 8-10 years of experience in the RTL-to-GDS flow and proficiency with EDA tools such as Fusion Compiler and PrimeTime...
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$125k - $145k
Job Title: Physical Design Engineer Salary Range: $125,000 - $145,000 per year (commensurate with experience) Location: USA Job Duration: Full... ...productize advanced RTL to GDS implementations through ASIC design flow. Lead the physical design closure process including...Permanent employmentFull timeRelocation- A leading technology firm in Santa Clara seeks an experienced engineer for GPU physical design. This role involves collaborating with teams to drive physical implementation, resolving design issues, and optimizing performance. The ideal candidate has over 10 years of experience...
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Cupertino, California, United States Hardware Description As a Physical Design engineer you will contribute to all phases of physical design of high... ...and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations...Relocation$210k - $250k
...the first silicon and system designed from the ground up for AI and... ...execution mode and has a world-class engineering team with decades of... ...Responsibilities Define the Physical Assembly of SOC. involving all... ...design by running all signoff flows such as Timing, Power, EM/IR,...
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