Wafer-Scale DFT Lead for Advanced SoCs

Conductor is seeking DFT engineers to contribute to and own DFT efforts for blocks and entire dies on wafer-scale A-0 and A-1 systems. You will drive test and diagnosis strategies to ensure high yield and robust design for cutting-edge hardware.

Ideal candidates will have experience leading DFT efforts for multiple advanced node SoC tapeouts and will bring expertise in multi-die and multi-chiplet designs, including AI accelerators.

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