Design Verification Engineer II

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsofts Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers clients and augmented reality.

We are looking for a design verification engineer to work in the dynamic Microsoft Artificial Intelligence S ilicon Engineering ( AIS iE ) team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environment.

Microsofts mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset innovate to empower others and collaborate to realize our shared goals. Each day we build on our values of respect integrity and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

TheAISiEsiliconteam isseekinga passionate driven and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. Weare responsible fordeliveringcutting-edge custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.

• Plan the verification of complex design IP/SoC interacting with the architecture and design engineers toidentifyverification test scenarios.

• Create and enhance constrained-random verification environments usingSystemVerilogand UVM or formally verify designs with SVA and industry leading formal tools

• Develop tests using UVM or C/C

• Analyse and debug test failures with designers to deliver functionally correct design.

• Identifyand write functional coverage for stimulus and corner cases.

• Close coverage to plug verification holes and meet tape out requirements.

• 3or more years of experience in design verification with a proventrack recordof delivering complex CPU or SoC IPs

• knowledge of verification principles testbenches stimulus generation and UVM or C based testenvironments.

• goodunderstanding of computer architecture

• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments

• Scripting language such as Python or Perl

This position will be open for a minimum of 5 days with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age ancestry citizenship color family or medical care leave gender identity or expression genetic information immigration status marital status medical condition national origin physical or mental disability political affiliation protected veteran or military status race ethnicity religion sex (including pregnancy) sexual orientation or any other characteristic protected by applicable local laws regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process read more about requesting accommodations.

Required Experience:

IC