Principal ASIC Design Engineer (Starshield)

Location Irvine, CA Company Overview SpaceX was founded under the belief that a future where humanity is exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. Position Title Principal ASIC Design Engineer (Starshield) Job Summary Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. You will develop cutting‑edge next‑generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe in a highly collaborative and fast‑paced environment, iterating rapidly from design and demo to operational capability. Responsibilities Design digital ASICs and/or FPGAs for Starshield projects. Evaluate architectural trade‑offs based on features, performance requirements and system limitations. Derive specifications for subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains. Define micro‑architecture, implement the RTL in Verilog/SystemVerilog, integrate at the top level and deliver a fully verified, synthesis/timing‑clean design. Work closely with the verification team to ensure all aspects of the design are covered and verified. Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check). Participate in silicon bring‑up and validation. Assist in the development of automated test lab equipment for lab measurements. Basic Qualifications Bachelor’s degree in electrical engineering, computer engineering, or computer science. 8+ years of experience in RTL implementation and/or FPGA/ASIC development. Preferred Skills and Experience Experience solving problems including clock domain crossings and power optimization. Experience with multicore CPU subsystem design. Experience with standard bus protocols (e.g. AXI, AHB). Experience with embedded processors. Experience with high‑speed and low‑power design techniques. Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera QuartusII). Ability to work in a dynamic environment with changing needs and requirements. Team‑player, can‑do attitude and ability to work well in a group environment while still contributing individually. Enjoy being challenged and learning new skills. Additional Requirements Ability to work long hours and weekends as necessary to support critical milestones. Willingness to travel for off‑site testing. Active TS‑SCI clearance may provide the opportunity to work on sensitive SpaceX missions; if so, subject to pre‑employment drug and random drug and alcohol testing. Compensation and Benefits Pay range: Principal ASIC Design Engineer: $200,000.00 - $285,000.00 per year Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on job‑related knowledge, skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program. Base salary is one part of your total rewards package at SpaceX. You may also be eligible for long‑term incentives in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will receive comprehensive medical, vision, and dental coverage, a 401(k) retirement plan, short and long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks. Employees accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law. To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. EEO Statement SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. EEO Compliance Contact Applicants wishing to view a copy of SpaceX’s affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process, should reach out to View email address on click.appcast.io. #J-18808-Ljbffr