Senior ASIC Timing Engineer — Lead Timing Closure
$136k - $218.5kNVIDIA
NVIDIA Corporation is seeking an ASIC Timing Engineer in Austin to lead timing analysis and closure for GPUs, CPUs, LPUs, and SoCs. You will collaborate with RTL, DFX, Clocks, and other teams to implement timing constraints, convergence strategies, and ECOs while advancing timing flows. A strong background in STA and sub-micron nodes is required. Base salary varies by level (136,000 USD - 218,500 USD for Level 3; 168,000 USD - 264,500 USD for Level 4) plus equity and benefits. #J-18808-Ljbffr NVIDIA Corporation
Vacancy posted 4 days ago
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