Senior Principal Engineer

Sr. Principal EngineerAbout ArmArm is the industry's leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address the performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, our technology is at the heart of a computing and connectivity revolution that continues to transform the way people live and businesses operate.The CPU Implementation team is part of Arm’s worldwide CPU development group. This diverse, engineering-focused team defines, designs, and builds Arm processor IP, collaborating with the world’s leading technology companies to enable innovation across billions of devices.Job OverviewWe are seeking a Sr. Principal Engineer to serve as a recognized technical authority for CPU physical implementation enablement and the translation of RTL optimization into measurable power, performance, and area gains in Solution Engineering and partner silicon. This senior individual contributor will shape technical direction and align BigA, Solution Engineering, partition owners, foundry-facing teams, and EDA partners around silicon-relevant outcomes.The role carries broad influence across Solution Engineering alignment, Cadence technology strategy, process-node enablement, and implementation-flow correlation. The ideal candidate combines deep CPU implementation and PPA expertise with exceptional technical judgment and the ability to lead through influence, converting complex tool, flow, and technology challenges into scalable capabilities that improve engineering effectiveness and silicon results.ResponsibilitiesSolution Engineering AlignmentAct as the senior technical authority connecting BigA RTL optimization with Solution Engineering implementation and partner-silicon outcomes. Establish an earlier and more durable engagement model across infrastructure tapeouts and mobile benchmark droplets using TSMC and Samsung foundry technologies. Shape the technical agenda, success measures, and operating mechanisms required to demonstrate that RTL feedback and resulting design changes deliver meaningful PPA improvement in downstream silicon contexts. Define the correlation and decision framework used to reconcile BigA and Solution Engineering implementation environments. Quantify recipe differences, aggressive implementation settings, and run-to-run variation; determine when deviations are technically justified; and ensure conclusions remain valid and silicon relevant. Create reusable evidence, guidance, and governance that allow teams to make consistent optimization decisions across designs, technologies, and partner use cases.EDA Tool Strategy and EngagementSet the technical strategy for engagement with Cadence across synthesis and place-and-route, representing the organization on the issues that most materially affect PPA, routing quality, correlation, runtime, and RTL feedback. Balance tactical interventions with strategic roadmap investments and define clear acceptance criteria for patches, durable fixes, and new capabilities. Create a disciplined qualification and deployment model that uses partition-owner expertise without diverting disproportionate effort from RTL optimization. Drive improvements that shorten feasibility-flow runtime while preserving fit-for-purpose accuracy, and ensure approved tool changes can be validated and released at scale. Translate advanced techniques, including SDP-based methods, into robust collateral that Solution Engineering and external partners can adopt to reproduce demonstrated PPA gains.Technology PortingOwn the technical framework for navigating asynchronous CPU and process-technology roadmaps. Establish how the organization evaluates node readiness, maintains useful RTL-feedback visibility when process collateral is incomplete, and optimizes RTL across the differing technology choices and schedules of infrastructure and mobile partners. Influence Solution Engineering and foundry-facing teams to engage earlier and accelerate delivery of stable, decision-quality PPA environments. Lead data-driven decisions on when to move to a new technology and when continued optimization on a mature node provides greater value. Define staged readiness, accuracy, and correlation criteria that make uncertainty explicit while enabling progress. Institutionalize repeatable porting practices that reduce bring-up time, remove recurring barriers, and preserve the relevance of RTL decisions as technology assumptions evolve.Flow Enablement and CorrelationProvide architectural and technical leadership for evolving the current Cadence-derived implementation flow toward strategic alignment with the Solution Engineering flow. Define the non-negotiable requirements for transition, including comparable PPA, reliable correlation, appropriate controls, debuggability, and the features needed to generate actionable RTL feedback. Guide the designated flow owner and cross-functional stakeholders toward a successful first infrastructure-core intercept planned for mid-2027. Establish a correlation and observability model that exposes recipe changes, tool variation, and unintended PPA shifts before they affect engineering decisions. Elevate usability through stronger diagnostics and adoption mechanisms, and define the path toward LLM-enabled interaction with implementation flows and databases. Use these capabilities to accelerate debugging, deepen root-cause analysis, and make institutional knowledge available at the point of engineering work.Required Skills and QualificationsBS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.15+ years of semiconductor industry experience with significant focus on CPU verification.Strong technical background in CPU verification methodologies and environments.Proven experience leading verification teams and large-scale engineering initiatives.Experience driving tooling, methodology, and flow transformations across organizations.Deep understanding of verification infrastructure, automation, regression systems, and front-end flows.Prior experience working closely with EDA vendors and managing strategic technical engagements.Existing relationships with major EDA vendors and ecosystem partners preferred.Demonstrated success driving adoption of new tools, flows, and engineering processes across teams on aggressive schedules.Experience leading and operating within global/distributed engineering teams.Strong communication, presentation, and stakeholder management skills.Ability to influence across organizations and drive alignment without direct authority.Ability to operate effectively across a diverse set of technical and organizational domains simultaneously.Strong execution mindset with passion, intensity, urgency, and a relentless drive for continuous improvement.Proven track record improving engineering efficiency while simultaneously improving quality of deliverables.Preferred QualificationsExperience driving AI/ML initiatives within semiconductor verification environments.Expertise in modern DevOps methodologies and scalable engineering infrastructure.Experience influencing verification technology roadmaps across large organizations.Strong understanding of verification productivity metrics and quality optimization strategies.Experience driving enterprise-scale process standardization and operational transformation initiatives.Experience aligning engineering workflows with centralized infrastructure and organizational platforms.At Arm, you will thrive in a highly stimulating and collaborative environment. You will be encouraged to share your ideas and experiences, while learning new skills from the best engineers in the world. We work in small teams, so your contributions are important, and your work will make a real difference!Salary Range:$308,600-$417,500 per yearWe value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.Accommodations at ArmAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email View email address on click.appcast.io. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.Hybrid Working at ArmArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.Equal Opportunities at ArmArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.