Senior Principal Design Engineer

The Senior Principal Solutions Engineer at Cadence is responsible for supporting the adoption of Cadence products to help chip designers achieve superior performance for their Design PPA goals. The role focuses on synthesis (logical and physical), place and route, and STA/SDC, with additional experience in tapeouts and multi‑voltage design implementation. Solutions engineers must articulate design methodologies involving Cadence tools and be proficient in the full Cadence tool portfolio. Responsibilities Own block implementation, top‑level implementation, and signoff‑focused efforts in Full Flow Services Projects. Lead the RTL‑to‑GDSII delivery of projects. Engage in competitive benchmarking on complex blocks, including CPUs, GPUs, and DSP cores, across multiple technology nodes on standard foundry solutions. Support regional customers and major customers (50%+ support). Assist customers in adopting Cadence front‑end tools in synthesis with Genus DFT & Scan with Encounter Test (ET) by providing methodology and tool knowledge to the IC design process, validated through successful design tapeouts. Drive best practices and lessons learned from evaluations/benchmarks and customer interactions back to product development and Cadence field engineers. Create and conduct technical presentations and product demonstrations to customers. Provide methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services. Assist sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications. Write and execute TCL/Perl scripts to achieve quick design automation solutions for customers. Qualifications Design experience should include ASIC design using Verilog. Senior‑level Application Engineer with deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis). Experience innovating with low‑power and multi‑voltage design techniques for leading‑edge wireless and mobile customers. Senior‑level Design Engineer supporting RTL‑to‑GDS implementation flows using Encounter Digital Implementation Platform. Manage strategic customer evaluations/benchmarks on Cadence's front‑end solutions to establish technology differentiation and assert Cadence competitive advantages. Manufacture multiple issues, set priorities, and explore new technologies. Must have a BS degree and at least 7 years of experience with strong technical knowledge of Cadence products. NOT AN ENTRY‑LEVEL POSITION. Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, veteran status, disability, or any other protected class. #J-18808-Ljbffr