Senior ASIC Verification Engineer - SystemVerilog/UVM
Teradyne Inc
Teradyne in North Reading, MA seeks an ASIC Verification Engineer to join the Reference Model team. You will verify complex ASIC/SoC designs using SystemC, SystemVerilog/UVM, and constrained-random methods, collaborating with design, firmware, and software groups.
The role emphasizes verification planning, testbench architecture, and delivering high-quality results with rigorous methodologies. Bachelor’s degree required; Master’s preferred, with 4+ years in semiconductor verification.
#J-18808-LjbffrVacancy posted 1 day ago
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