Senior ASIC Power Architect for ML Accelerators
Google is shaping the future of AI/ML hardware acceleration through TPU power design, delivering efficient, scalable silicon for world‑class AI workloads. You will drive power modeling, implement novel optimization techniques, and contribute to RTL low‑power practices within a cutting‑edge TPU architecture team. You will collaborate across hardware and software groups to meet dynamic power targets and deliver robust, power‑aware designs, enabling high‑performance AI systems at scale. #J-18808-Ljbffr Google
Vacancy posted 1 day ago
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