Principal Engineer-HIG HBM Architecture

Job Title & Req ID JR90853 Principal Engineer - HIG HBM Architecture Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Job Profile(s) Systems Design Engineer 4 – Systems Design Engineering MTS Responsibilities Develop innovative memory subsystem architectures for HBM-based AI/ML solutions, including PHY, memory controllers, NOC, microcontrollers, MBIST, interfaces, adapters, RAS, and support for DDR/LPDDR/HBM memory types. Define Memory and RAS architecture requirements and drive end‑to‑end architectural specification for next‑generation memory subsystems. Collaborate with internal and external partners to develop novel architectures and detailed IP requirements across all memory subsystem components. Lead engagement with IP vendors, including evaluation and selection of interface IP and functional IP blocks. Analyze benchmarks, workloads, and simulation results to identify performance and efficiency innovation opportunities in memory subsystems. Perform performance and performance/Watt modeling; estimate gate count, power, and area; and generate architectural and external-facing specifications aligned with hardware/protocol standards. Partner with RTL, validation, and multi‑functional teams to ensure successful and timely implementation of subsystem features, contributing to technical reviews for HBM and memory products. Drive microarchitecture definition, participate in performance simulation, benchmarking, and debug issues across high‑level models, RTL simulation, and hard/soft IP. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 10 years of experience in memory subsystem architecture and design. Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM). Experience with PHY design and understanding of signal integrity issues. Proficiency in Network‑on‑Chip (NoC) architecture and design. Familiarity with industry‑standard bus protocols such as AXI, AMBA, AHB, DFI, HIF, etc. Strong analytical and problem‑solving skills. Excellent written and verbal communication skills. Preferred Qualifications A PhD in a relevant field, or equivalent experience. Familiarity with EDA tools for design and verification. Practical experience with multi‑core systems, coherent interconnects, and industry IO protocol like PCIe/CXL, confidential compute, virtualization & security. Knowledge of serial link protocols (UCIe, etc.) is desired. Salary The US base salary range Micron estimates for this full‑time position is $146,000.00 – $309,000.00 a year. Additional compensation may include bonuses and equity. EEO Statement Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr