Design Verification Engineer

Job Description Renesas is seeking a New College Graduate (NCG) Design Verification Engineer to join the CIP organization and contribute to the verification of complex mixed‑signal power management ICs. This is an excellent opportunity for a motivated recent graduate to develop foundational skills in design verification within a dynamic, collaborative engineering environment. The ideal candidate is eager to learn, detail‑oriented, and has a solid academic background in electrical or computer engineering. Location: 100% onsite. Local candidates preferred. Entry level: BS with up to 2 years experience or MS with no experience in Electrical Engineering, Computer Engineering, or a related field. Key Responsibilities Collaborate with Digital, Analog, and Verification teams on system requirements Participate in the development of Verification Plans and Environments Develop and verify self‑checking testbenches using Verilog and SystemVerilog Write and execute directed and constrained‑random tests to improve coverage Enhance test coverage, efficiency, and overall effectiveness of the verification process Debug and report design issues; drive root‑cause analysis with design teams Learn and apply verification methodologies including UVM under senior guidance Support regression runs and analyze simulation results Document test plans, results, and findings clearly and accurately Grow technical skills and contribute to team and project goals Qualifications BS with up to 2 years experience or MS with no experience in Electrical Engineering, Computer Engineering, or a related field Coursework or project experience with digital design, verification Familiarity with Verilog or SystemVerilog Basic understanding of analog and digital circuit concepts Strong analytical, problem‑solving, and debugging skills Good written and verbal communication skills; ability to work in a team environment Preferred Qualifications Exposure to UVM (Universal Verification Methodology) through coursework, projects, or internships Understanding of power electronics concepts (DC‑DC converters, LDOs, PMICs) is a plus Experience or coursework involving simulation tools such as Cadence Virtuoso Familiarity with scripting languages such as Python or Perl Familiarity with Real Number Modeling (RNM) or Verilog‑A Modeling concepts Internship or research experience in VLSI design, verification, or a related field EEO Statement Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. Renesas Electronics deals with dual‑use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas. #J-18808-Ljbffr Renesas Electronics Corporation