Senior CAD Engineer

Position Senior CAD Engineer (San Jose, CA) W2 contract position; not eligible for C2C or W2 referral candidates. Job Overview We are seeking a Senior IC EDA/CAD Engineer to own and advance our EDA design flows, IT infrastructure, and signoff methodologies. This individual will serve as the technical authority for the EDA environment, driving the setup, qualification, and maintenance of advanced FinFET process technologies while supporting analog, mixed‑signal, RF, high‑speed I/O, and digital SoC development. The ideal candidate will play a critical role in enabling first‑time‑right silicon through the deployment and support of industry‑standard backend verification and signoff flows. Key Responsibilities EDA Environment & PDK Management Install, qualify, and maintain advanced foundry PDKs for leading‑edge FinFET technologies (2 nm, 3 nm, and 5 nm nodes). Manage and optimize EDA infrastructure, including compute clusters, grid utilization, and software license management. Ensure a stable, scalable, and efficient design environment across engineering teams. Analog, Mixed‑Signal & Digital Design Flow Development Develop, deploy, and support end‑to‑end Cadence design flows, including Virtuoso and Innovus environments. Optimize design methodologies for RF, analog, mixed‑signal, and high‑speed I/O applications. Standardize design processes to improve productivity and design quality. Physical Verification & Signoff Create, automate, and maintain chip‑level and IP‑level signoff flows. Support physical verification using Siemens Calibre for DRC, LVS, and PERC verification. Manage parasitic extraction methodologies using Synopsys StarRC to ensure signoff accuracy. Reliability Verification Deploy and support advanced reliability verification methodologies, including: Electro‑Migration and IR‑Drop (EMIR) analysis Programmable Electrical Rule Checking (PERC) Ensure reliability and manufacturability requirements are met for advanced process technologies. Automation & Technical Support Develop scripts, utilities, and automation frameworks to streamline workflows and eliminate manual processes. Standardize EDA flows across projects and improve tool interoperability. Serve as the primary technical interface with EDA vendors, driving issue resolution and roadmap alignment. Qualifications Required Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 5+ years of hands‑on IC CAD/EDA engineering experience. Direct experience supporting advanced FinFET technologies (5 nm, 3 nm, or 2 nm nodes). Deep expertise with: Siemens Calibre (DRC, LVS, PERC) Synopsys StarRC Cadence Virtuoso and Innovus Strong scripting and automation skills using: SKILL Perl Python Tcl Bash/Shell Strong Linux administration and troubleshooting skills. Experience managing compute clusters and grid environments (LSF, SGE, or similar). Experience with version control and design data management tools such as Perforce or ICManage. Preferred Knowledge of advanced‑node design challenges, including: Multi‑patterning Dummy fill effects Layout‑dependent effects (LDE) Design for Manufacturability (DFM) signoff Background in custom layout or circuit design. Experience working directly with foundries on: Design rule waiver requests PDK issue reporting Process qualification activities Strong analytical, troubleshooting, and problem‑solving abilities. Excellent communication and collaboration skills with cross‑functional engineering teams. Hours Monday through Friday; 8 am - 5 pm CST Compensation $90-$100 per hour Contact Hannah Wilson at View email address on click.appcast.io. You can also schedule an appointment to learn more about this opportunity. #J-18808-Ljbffr