AR/VR iOS Developer

Meta is seeking a Hybrid ASIC Power Engineer to join our team in Sunnyvale, CA, focusing on power analysis and optimizations for our AR/VR products. The ideal candidate will have extensive experience in ASIC power engineering, particularly in machine learning applications, and will be proficient in Python, Tcl, and SystemVerilog. Responsibilities: Conduct RTL and netlist level power analysis. Post-process and script report log files for data analysis and format conversion. Set up, run, debug, and analyze ASIC flows including Synthesis, PD, Power, and Timing. Implement RTL and UPF for specific blocks. Document and communicate findings clearly. Qualifications: 10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer. Experience with power estimation tools and synthesis, along with some physical design knowledge. Understanding of power trade-offs in design and back-end implementation. Hands‑on experience in scripting and data analysis. BS in Electrical Engineering, Computer Science, or equivalent experience. Skills: Proficiency with Synopsys tools (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules). Scripting skills in Python, Perl, or similar for data post-processing. Experience in low power design methodologies, including UPF specifications. Tell us what you're building and we'll recommend qualified vendors for your project. ASIC Design Services Verification Packaging & Wafer Semiconductor IP Find the Right Semiconductor Partner Tell us what you're building and we'll recommend qualified vendors for your project. ASIC Design Services Verification Packaging & Wafer Semiconductor IP Free No obligation Response within 24 hours #J-18808-Ljbffr