Senior ASIC Design Verification Engineer

Working remotely, the full-time Senior ASIC Design Verification Engineer will verify the functionality and performance of custom silicon designs, defining verification approaches and collaborating with cross-functional teams to ensure robust design validation. Key responsibilities Develop and execute verification plans for various levels, building SystemVerilog/UVM test benches and integrating formal verification Drive testing strategies to validate functionality and corner cases, managing regression testing and simulation farms for efficient test throughput Collaborate with architecture and design teams, participating in design reviews and influencing design-for-verification best practices Required qualifications B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field 5+ years of experience in ASIC/SoC verification with a solid understanding of SystemVerilog and digital logic Proficiency in simulation tools (VCS, Xcelium, Questa) and scripting languages (Python, Perl, TCL) Experience with UVM-based testbench development, constrained-random testing, and functional coverage Understanding of industry-standard interfaces (e.g., APB/AHB/AXI) and familiarity with embedded processor-based designs