FPGA Engineer

Science is a clinical stage, vertically integrated technology company focused on solving some of neuroscience’s hardest questions and most serious unmet medical needs. We work to restore quality of life to those with debilitating conditions for which there are no treatment options, creating devices aimed at restoring vision, cognition, and mobility to patients who have lost it. To support progress across our industry, we provide state-of-the-art components and vertically integrated infrastructure for others to build on via Science Foundry. Field Programmable Gate Array (FPGA) Engineer (Science Corporation; Alameda, CA): Design, develop and test Field Programmable Gate Array (FPGA) systems using Amaranth HDL, Verilog, System Verilog, and cocotb, UVM (Universal Verification Methodology) for verification of designs. Collaborate with multi-disciplinary teams to define requirements and specifications. Contribute to the evolution of our development methodologies and processes. Perform functional and timing verification of FPGA designs. Perform hardware bring-up of FPGA designs and electronic systems. Develop digital communication interfaces for both custom ASICs and off-the-shelf devices. Develop control and configuration circuits to manage custom ASICs. Create low-latency, high speed computer engines for various applications including neural signal processing. Develop FPGA-based controllers for custom wireless connectivity solutions. Debug, troubleshoot and resolve hardware-related issues in prototyping, production, failure analysis, and field returns. Contribute to the evolution of the company’s development methodologies and processes. Minimum requirements Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, Computer Science, or related field, plus three (3) years of experience as a FPGA Engineer or related occupation. Must have experience with the following: gateware development delivering reliable, readable, and maintainable gateware; FPGA design processes and tools: LUTs, slack, pipelining, clocking (across domains and buffering), metastability, synthesis, and scripting (Python and TCL); and interfacing with microsystem sensors and actuators. Salary: $167,000 – $200,000 per year #J-18808-Ljbffr Science