Principal CPU PPA Pathfinding Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > CPU Engineering

General Summary:

Define competitive PPA options that will shape Qualcomm's future CPU products.

Role Overview

As a Principal CPU PPA Pathfinding Engineer, you will analyze, define, and evaluate power, performance, and area options for future Qualcomm CPU projects. You will combine deep CPU implementation expertise with competitive analysis to translate architectural concepts, competitor and industry insights, process technology choices, design methodologies, and physical design constraints into credible PPA projections and actionable recommendations. You will develop and compare multiple CPU design options, clearly articulate their product-level trade-offs, and propose preferred directions to CPU Leads and CPU Product Managers. Your work will influence early CPU definition, implementation strategy, roadmap choices, and product competitiveness across multiple market segments.

Key Responsibilities

• Lead CPU PPA pathfinding studies for future projects, from early concept exploration through implementation feasibility assessment.
• Define and compare PPA options across CPU microarchitecture, frequency targets, process technology, standard-cell libraries, voltage operating points, floorplans, clocking strategies, and implementation methodologies.
• Build representative implementation experiments and design-of-experiment frameworks to quantify trade-offs and identify the highest-value optimization opportunities.
• Generate area and power estimates, frequency projections, and complete power-performance curves across representative CPU workloads, voltage-frequency operating points, process and library options, and thermal conditions.
• Develop constrained-performance projections under defined platform and product limits, including peak-power, sustained-power, thermal, voltage, frequency, area, and cost constraints.
• Evaluate iso-power, iso-performance, iso-area, and thermally constrained operating points to quantify option-level efficiency and identify the most competitive design point for each product segment.
• Partner with Performance, Power, Thermal, SoC, and Product teams to establish workload assumptions and system power boundaries, and translate CPU power-performance curves into sustained product-level performance projections.
• Partner closely with CPU Architecture, RTL, Performance, Power, Circuits, Physical Design, CAD, Process Technology, SoC, Thermal, and Product teams to align assumptions and recommendations.
• Drive data quality, correlation, and consistent PPA evaluation methodologies across projects, tools, and technology nodes.
• Communicate complex trade-offs clearly to technical leaders and partner teams, and provide recommendations that guide CPU project selection and execution.
• Mentor engineers and contribute to scalable PPA analysis flows, automation dashboards, and best practices.
• Own competitive CPU PPA analysis across relevant market segments, using available benchmark results, power-performance data, performance-per-area metrics, die analysis, published architecture information, and technology assumptions to identify competitive gaps and opportunities.
• Build normalized, apples-to-apples comparisons that account for workload, operating point, process node, library, metal stack, system power boundary, thermal constraints, and measurement or modeling methodology.
• Translate competitive insights into forward-looking PPA targets, design requirements, and differentiated implementation strategies for future Qualcomm CPU generations.
• Develop multiple viable CPU PPA options and propose them to CPU Leads and CPU Product Managers, including quantified benefits, risks, assumptions, product-KPI impact, implementation complexity, schedule implications, and a clear recommendation.
• Partner with CPU Product Management to connect engineering trade-offs with customer priorities, market positioning, product tiers, cost constraints, sustained performance, benchmark leadership, and real-world workload efficiency.
• Maintain a fact-based view of competitive trends and technology trajectories, and refresh recommendations as competitor data, silicon measurements, product requirements, and process assumptions evolve.

Required Skills

• 15+ years of relevant industry experience in CPU or high-performance ASIC/SoC implementation.
• Strong hands-on implementation background, including physical synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, power analysis, and signoff.
• Demonstrated experience evaluating and optimizing power, performance, and area for high-frequency CPU cores or similarly complex designs.
• Strong understanding of CPU implementation trade-offs, critical paths, physical constraints, low-power techniques, and advanced-node design challenges.
• Ability to design controlled experiments, analyze large data sets, distinguish first-order effects from noise, and convert results into clear engineering recommendations.
• Proficiency in scripting and automation using Python, Tcl, Perl, or similar languages.
• Excellent technical communication, cross-functional collaboration, and problem-solving skills.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Preferred Qualifications

• Experience with CPU microarchitecture and performance analysis, including the relationship between workloads, critical paths, frequency, power, and area.
• Experience with advanced process nodes and technology pathfinding, including standard-cell library, voltage, interconnect, and physical design trade-offs.
• Hands-on experience with industry-standard implementation and signoff tools from Cadence and/or Synopsys.
• Experience developing PPA estimation models, power-performance curves, design dashboards, or automated experiment frameworks.
• Knowledge of power modeling, thermal constraints, multiple power domains, UPF-based implementation, and low-power optimization techniques.
• Optional: experience with pre-silicon to post-silicon PPA correlation, silicon characterization, or using measured silicon data to improve future projections.
• Experience influencing technical direction across architecture, implementation, methodology, and product teams.
• Experience performing competitive CPU analysis, including power-performance curves, performance per watt, performance per area, die-level analysis, or normalized product comparisons.
• Experience presenting complex technical options and recommendations to CPU leadership, product management, or senior cross-functional decision makers.

What Success Looks Like

• Future CPU projects begin with well-supported PPA targets, implementation assumptions, and clearly understood trade-offs.
• Key architecture, technology, and implementation options are evaluated early enough to influence project direction.
• PPA projections are repeatable, data-driven, and increasingly correlated across design stages.
• Cross-functional teams can make faster, higher-confidence decisions using your analysis and recommendations.
• Competitive gaps are identified early and converted into measurable CPU PPA targets and prioritized engineering actions.
• CPU Leads and CPU Product Managers receive decision-ready options with transparent assumptions, quantified trade-offs, risks, and a recommended path.
• CPU Leads and CPU Product Managers can compare options using consistent power-performance curves and constrained-performance projections tied to product operating limits.

Why Join This Role

This is a high-impact Principal-level position with the opportunity to shape the technical direction of next-generation Qualcomm CPUs. You will operate at the intersection of architecture and silicon implementation, solve complex pathfinding problems at advanced nodes, and directly influence performance leadership, power efficiency, area competitiveness, and execution readiness.

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Pay range and Other Compensation & Benefits

• $216,600.00 - $325,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.