Engineering Manager, Hardware Platform Security - Anthropic

About the role Platform Security Engineering (PSE) sits within Data Center Security Engineering (DCSE). As Anthropic expands beyond traditional cloud providers into owned facilities, colocation, and partner sites, we take on the security responsibilities that cloud providers used to abstract away: firmware integrity, boot chain verification, platform trust, and host hardening. PSE exists so that Anthropic can deploy training and inference workloads to any qualified environment with a demonstrable security posture, including the technical controls behind our AI Safety Level commitments. We are hiring an engineering manager to lead a group of platform security engineers covering firmware research, OS and kernel hardening, platform trust integration, and server manageability firmware. You will own the roadmap for this group, grow the team, and be accountable for the security posture of the compute platforms Anthropic runs on: hardware roots of trust, secure and measured boot, attestation, firmware supply chain, and the integrity of the hosts that hold model weights on bare-metal infrastructure. This is a hands-on management role. You will not write most of the code, but you will review designs, make the final call on hard trade-offs, and be able to reason with your engineers from a silicon root of trust through firmware, bootloader, kernel, and host software. You will partner with infrastructure, fleet, and compute teams inside Anthropic, and with silicon vendors, OEMs, and compute providers outside it. You will report to the Data Center Security Engineering manager. Key responsibilities Lead and grow the platform security engineering group: hiring, onboarding, development, performance, and prioritization for full-time engineers, and coordination of contractor and vendor engineers working alongside them Own the platform security roadmap and its delivery: hardware root of trust and attestation, secure and measured boot across CPU, BMC, accelerator, and peripheral firmware, OS and kernel hardening, and the host-side pipeline that turns attestation evidence into production gates Own the firmware supply chain posture for the fleet: SBOM and reference integrity manifests, authenticated update, rollback protection, and the vendor relationships needed to get fixes shipped Drive platform risk assessments for new compute platforms and providers, and make evidence-based go/no-go recommendations with bounded risk rather than perfect-or-nothing gates Partner with infrastructure, fleet, compute, and detection and response teams so that platform controls land in production without degrading training or inference performance Manage relationships with silicon vendors, OEMs, and compute providers: security requirements, vulnerability management, disclosure and remediation timelines, and upstream and standards-body engagement (TCG, OCP, IETF) #J-18808-Ljbffr Polluxa, Inc.