CPU Cache Architect

AMD Cores Organization Fellow-Level Design Engineer

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

AMD's Cores Organization delivers industry leading CPU's and caches that are the foundation of AMD's server, client, and gaming business. We are looking for a Fellow-level experienced design engineer to join this innovative team as a technical expert and work in the areas of performance modeling, performance analysis, and microarchitecture development. The candidate will be a key contributor and leader for AMD's next generation cores and caches. The candidate will join the team based in Austin, TX.

The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details. We work on programs with long timelines, so self-motivation and a commitment to meeting deadlines is required. We are pushing the envelope on chip performance, so the status quo must be challenged on every program. This requires creativity and innovation, but also excellent verbal and written communication skills. We work in small teams, but we are part of a large cross-site Core's organization, so teamwork is also vital to our success.

Key responsibilities:

• Collaborate with a small, dedicated team of hardware and software engineers to optimize the performance of CPUs, caches, and interconnect.
• Develop and enhance cycle-accurate core, cache, and SoC (System on a chip) performance simulators.
• Develop other simulators at different abstraction levels.
• Use those simulators as well as analytical methods, emulation, and post-silicon observation and experimentation to develop and evaluate microarchitecture improvements.
• Develop and improve tools and methodology for performance analysis of workloads.
• Guide and mentor junior engineers.

Preferred experience:

• C++ programming and scripting language capabilities
• Computer architecture background with industry experience in architecting processors, caches, and interconnect.
• Familiarity with Digital RTL Design, Software Development, Verilog HDL. Experience writing and debugging RTL.
• Experience collaborating effectively towards the success of a project by working closely with a diverse team across disciplines.

Academic credentials:

• BS/MS/PhD in EE, CS, CSE (or similar), and expertise in hardware design

Location: Open To Remote