Senior ASIC Design Engineer - RTL/Analog & Python
Tokyo Electron Limited
Tokyo Electron Limited is seeking a Senior ASIC Design Engineer in Austin, TX, to support the design and verification of VLSI test chips. This role requires proficiency in Python for automation of EDA workflows and strong collaboration across teams. Ideal candidates will have a Bachelor's degree in Electrical Engineering or a related field, with significant industry experience. The position offers educational reimbursement for continued skill development and a commitment to diversity and equal opportunity in the workplace. #J-18808-Ljbffr Tokyo Electron Limited
- NVIDIA AI in Austin, TX is looking for an ASIC Design Engineer to join its System-On-Chip group. In this role, you will focus on improving methodologies... ...strong coding skills in scripting languages like Perl or Python. NVIDIA offers competitive salaries and a supportive,...SeniorPython
- ...illness. The Role As a Senior Digital Design Engineer, you will translate... ..., synthesizable RTL that forms the foundation... ...cleanly from FPGA to ASIC. Responsibilities... ...with digital control of analog/mixed‑signal IP,... ...reports. Scripting in Python/Tcl/Perl for automation...SeniorPython
- ...America, Inc. is seeking a ASIC Design Engineer, Senior to support the design, layout... ...of VLSI test chips, using Python to automate EDA workflows... ...silicon verification, including RTL simulation and functional... ....* Contribute to RTL and analog block design and verification...SeniorPythonWork at office
$136k - $218.5k
...NVIDIA System‑On‑Chip (SOC) group as an ASIC Design Engineer and make a broad impact while working... ...delivering system‑level methodologies and RTL to measure performance on the industry'... ...and strong coding skills in Perl/Python or other industry‑standard scripting languages...SeniorPython$136k - $218.5k
...ID: JR2008535 Job Category: Engineering Time Type: Full time Join the... ...-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact... ...-level methodologies and RTL to measure performance on the... ...strong coding skills in Perl/Python or other industry-standard scripting...SeniorPythonFull time$136k - $212.75k
Senior ASIC Physical Design Engineer, Netlisting page is loaded## Senior ASIC Physical Design Engineer, Netlistinglocations... ...checking/FV required from RTL to tapeout with industry-standard... ...languages, such as, Perl, TCL, Make, Python, etc.**Ways to stand out from the crowd...SeniorPythonShift work- A leading technology company in Austin is seeking an ASIC Design Engineer to join their team. The role focuses on defining and delivering... .... Candidates should have programming experience in Python, knowledge of Verilog RTL design, and excellent problem-solving skills. The...Python
- SpaceX is looking for a motivated Sr. RTL Design Engineer to develop next-generation ASICs for applications in space and ground infrastructures. The ideal candidate will have a Bachelor’s degree in a relevant field and over 5 years of RTL design experience. Responsibilities...Senior
- ...technology company specializing in brain-computer interfaces is seeking a Senior Digital Design Engineer. In this role, you will define digital microarchitectures, write high-quality RTL for FPGAs and ASICs, and own the FPGA implementation process from synthesis to timing...Senior
- .## ASIC RTL Design EngineerAustin,Texas,United States## Grow with us to find all you need to... ...About this opportunity:****ASIC RTL Design Engineer** Hybrid work schedule This is not a... ...design Strong command of C/C++, TCL, and/or Python Proficiency in SystemVerilog, Verilog,...PythonTemporary work
- ...thinking team of architects, engineers, and business professionals... ...Networks is seeking talented Senior ASIC Design Engineers with deep... ...Responsibilities: ~ Implement RTL designs using Verilog/System... ...scripting languages such as TCL, Python, or Perl. ~...SeniorPythonRemote jobFull timeFlexible hours
$168k - $264.5k
NVIDIA Corporation is seeking a Senior ASIC RTL Integration and Netlisting Engineer in Austin, Texas. This role drives high-frequency and low-power design integration and netlisting for CPUs, GPUs... ...in scripting languages like Python or TCL. NVIDIA offers a competitive...SeniorPython$136k - $218.5k
...technology company in Austin, Texas is seeking an experienced ASIC Design Engineer to join the SOC group. The role involves defining, developing... ...and delivering methodologies for system-level IP, debugging RTL checks, and working collaboratively with diverse teams. Candidates...Senior- ...Devices, Inc. is hiring an SMTS Silicon Design Engineer in Austin, Texas. The role involves designing... ...semiconductor components, focusing on ASIC development and collaboration with cross... ...in Verilog, System Verilog, and Python. No travel is required for this position...SeniorPython
- ...established industry player seeks a skilled engineer with extensive experience in SoC design and integration of various... ...in scripting languages like Python. Join a dynamic team where your expertise... ...an impact, this opportunity is perfect for you. #J-18808-Ljbffr Core AsicSeniorPython
- Cadence Design Systems is seeking a Senior Principal Design Engineer to support chip designer customers in Austin. This role focuses on utilizing Cadence tools to... ...achieve superior design performance, specifically in ASIC design using Verilog and managing evaluations on...Senior
- ...you'll contribute to designing, optimizing, and manufacturing... ...As a Cellular ASIC Design Engineer, you'll develop and optimize... ...- Understand RTL to GDS digital flow and... ...timing paths (digital, analog, mixed signal) and timing... ...programming skills (Python, Perl, TCL, Unix shell...Python
$106.5k - $162k
A leading semiconductor foundry in Austin, TX is seeking a Senior Engineer, Physical Design (ASIC/SoC Place & Route). This role involves the entire APR implementation flow from RTL-to-GDS, working in a hybrid model with 4 days in the office. Candidates should have a Master...SeniorWork at office$116k - $189.75k
ASIC Design Efficiency Engineer page is loaded## ASIC Design Efficiency Engineerlocations: US, CA, Santa Clara... ..., area and power efficient RTL to achieve design targets.* Collaborate... ...design experience* Scripting knowledge in Python/PerlNVIDIA is widely considered to be...Python- ...results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world... ...while introducing mixed-signal and analog circuit design and features. You will work... ...techniques Scripting languages (Perl, Python) Formal verification and low-power design...Python
$120k - $225k
...Description We’re hiring experienced RTL Design Engineers to play a key role in designing and implementing... ...of AI computing with breakthrough analog technology that delivers 100× the... ...architectures. Strong scripting ability (Python or similar) for design automation and...SeniorPythonNight shift$116k - $189.75k
...world.We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and... ...checking/Formal Verification required from RTL to tapeout with industry-standard... ...languages, such as, Perl, TCL, Make, Python, etc.Ways to stand out from the crowd:...Python- Ericsson GmbH is looking for an ASIC RTL Design Engineer based in Austin, Texas. In this hybrid role, you'll be pivotal in designing the custom silicon that powers next-generation 5G networks. You will collaborate across disciplines, work on RTL design, and optimize complex...
$120k - $225k
We’re hiring experienced Design Verification Engineers to play a key role in developing... ...with breakthrough analog technology that delivers 10... ...engineers collaborate closely with RTL design, architecture... ...Strong scripting skills (Python or similar) for automation...SeniorPython- Cisco Systems is looking for a Physical Design Engineer in Austin, Texas. This role focuses on the technical execution of high-performance ASIC designs, including the RTL-to-GDSII implementation flow for advanced nodes. The ideal candidate will have a Bachelor's degree...
- PMU Design Verification Engineer: Analog & Mixed Signal Engineer Did you know that Apple is hiring analog & mixed... ...a combination of analog circuits and RTL in the same simulation.... ...but are not limited to, TCL, Skill, Python, and/or PERL. Your familiarity with...Python
$220.92k - $311.89k
**Welcome!**.Principal Design Engineer - AI SoC / Subsystem Lead page is loaded##... ....* ## Microarchitecture & RTL Development: Define and... ...design and implementation for ASIC/SoC development.## **Preferred... ...## Proficiency in scripting (Python, TCL, etc.) for automation and...SeniorPythonLocal areaImmediate startShift work- .## ASIC Design Verification EngineerAustin,Texas,United States## Grow... ...networks — and the verification engineers who prove they work are the... ...of hands-on, in industry RTL verification experience in IP... ...Scripting proficiency — TCL, Python, Perl, or equivalent Clear, confident...PythonTemporary workWorldwide
$136k - $212.75k
...group is looking for an experienced ASIC Verification Engineer! In this position you will have the chance... ...methodologies for the corresponding design (RTL). For this position, you should have... ...programming. Strong coding skills in Python or other industry-standard scripting...SeniorPython- ...in Austin, Texas, is seeking a Custom Design Automation Engineer. You will automate analysis flows, manage... ...languages like SKILL, Perl, Python, TCL, and Shell. Join a pioneering silicon... ...contribute to groundbreaking projects focused on ASIC designs. #J-18808-Ljbffr Apple Inc.SeniorPython
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