Senior Director, Physical Design & Backend Engineering (HPC)

Job Description

Job Description

• Location: Austin, TX (On-site)
• Department: Engineering – Semiconductor / Hardware Engineering
• Employment Type: Full-Time
• Base Salary: $260,000 – $290,000 USD
• Annual Performance Bonus: Target bonus of 30%
• Competitive sign-on bonus and equity package
• Comprehensive benefits package

Visa sponsorship is not available for this position. Applicants must be authorized to work in the United States without current or future sponsorship.

The Opportunity

We are partnering with a global semiconductor leader developing next-generation High-Performance Computing (HPC), AI, Automotive, and advanced System-on-Chip (SoC) technologies.

We are seeking an accomplished Senior Director, Physical Design & Backend Engineering to lead a large, globally distributed backend engineering organization responsible for delivering complex HPC SoCs from RTL through GDSII and tape-out.

This executive leadership role is accountable for end-to-end backend execution across multiple concurrent silicon programs, ensuring successful delivery of high-quality silicon that meets aggressive Power, Performance, and Area (PPA) targets.

The successful candidate will already be operating at the Senior Director level within a leading semiconductor organization and have demonstrated ownership of large global engineering teams, advanced-node silicon delivery, and organization-wide backend execution.

This is an exceptional opportunity for an executive who has progressed from hands-on physical design engineering into senior organizational leadership while successfully scaling global backend organizations responsible for complex SoC implementation.

What You'll DoLead End-to-End Backend Execution

Own complete RTL-to-GDSII implementation across multiple concurrent HPC SoC programs.

Lead all aspects of backend implementation including:

• Logic synthesis
• Floorplanning
• Place & Route (PnR)
• Clock Tree Synthesis (CTS)
• Timing Closure
• Physical Verification
• Signoff
• Tape-out

Ensure predictable execution, milestone adherence, and first-pass silicon success.

Drive engineering excellence while balancing schedule, quality, cost, and aggressive Power, Performance & Area (PPA) targets.

Lead a Global Backend Engineering Organization

Lead and scale large globally distributed backend engineering organizations across multiple international locations.

Provide executive leadership for engineering managers, technical leaders, and backend engineering teams.

Establish engineering standards, execution frameworks, accountability, and delivery ownership across multiple sites.

Develop future engineering leaders while fostering a culture of technical excellence, accountability, and collaboration.

Own Silicon Delivery

Own successful delivery of multiple concurrent advanced-node SoC programs.

Drive:

• Execution predictability
• Silicon quality
• PPA optimization
• Schedule adherence
• Design convergence
• Manufacturing readiness

Ensure all programs meet signoff criteria before tape-out.

Drive Technology & Methodology Excellence

Lead continuous improvements in backend methodologies, implementation flows, automation, and engineering productivity.

Partner closely with:

• Architecture
• RTL Design
• DFT
• Product Engineering
• Methodology
• Program Management
• Silicon Validation
• Foundry partners
• EDA vendors

Champion scalable engineering practices that improve delivery quality across multiple engineering organizations.

Organizational Leadership

Standardize engineering methodologies across global backend teams.

Develop KPIs, engineering metrics, dashboards, and execution processes that improve visibility and predictability.

Identify execution bottlenecks while continuously improving organizational capability.

Drive operational excellence across multiple engineering sites.

Scope & Impact

In this role you will:

• Own backend execution across multiple advanced-node HPC SoC programs.
• Lead large globally distributed backend engineering organizations.
• Influence silicon delivery schedules, engineering quality, and business outcomes.
• Drive engineering methodology improvements across multiple organizations.
• Shape the long-term execution capability of the company's backend engineering organization.

What We're Looking ForEducation

Master's degree in Electrical Engineering, Computer Engineering, or related technical discipline preferred.

Bachelor's degree with extensive semiconductor industry experience will also be considered.

Experience

The ideal candidate will bring:

• 20+ years of semiconductor industry experience.
• Current or recent Senior Director-level experience leading Physical Design & Backend Engineering organizations.
• Proven ownership of complete RTL-to-GDSII delivery across multiple concurrent SoC programs.
• Demonstrated experience leading large globally distributed engineering organizations.
• Experience delivering multiple advanced-node tape-outs (5nm, 3nm, or similar).
• Proven success meeting aggressive PPA, quality, and schedule objectives.
• Experience working across multiple global engineering sites and cultures.
• Experience leading engineering managers and senior technical leaders, not solely individual contributor teams.

Technical Expertise

Deep expertise in:

• RTL-to-GDSII implementation
• Physical Design
• Backend Engineering
• Logic Synthesis
• Floorplanning
• Place & Route (PnR)
• Clock Tree Synthesis (CTS)
• Timing Closure
• Physical Verification
• Design Signoff
• Tape-out Execution
• Advanced-node implementation
• Power, Performance & Area (PPA) optimization
• Backend methodology development
• Physical implementation automation

Experience collaborating with major semiconductor foundries and EDA vendors is highly desirable.

Leadership Capabilities

The successful candidate will demonstrate:

• Executive leadership of large globally distributed engineering organizations.
• Strong ownership of backend execution across multiple concurrent silicon programs.
• Proven ability to lead through engineering managers and senior technical leaders.
• Cross-functional collaboration across Architecture, RTL, DFT, Product Engineering, Program Management, and executive leadership.
• Data-driven decision-making using engineering KPIs and execution metrics.
• Success building, mentoring, and retaining world-class engineering teams.
• Demonstrated ability to drive organizational change and execution excellence at scale.

Preferred Qualifications

Experience in one or more of:

• High-Performance Computing (HPC)
• AI Accelerators
• Automotive SoCs
• Networking Silicon
• Mobile Processors
• Advanced SoCs

Additional experience with:

• Organization-wide backend methodology development
• Backend flow optimization
• Engineering process standardization
• Multi-site engineering leadership
• Advanced-node silicon implementation

is highly desirable.

Key Success Measures

Success in this role will be measured by your ability to:

• Deliver advanced-node silicon programs on schedule.
• Achieve aggressive PPA and quality targets.
• Drive first-pass silicon success.
• Improve execution predictability and engineering cycle times.
• Scale global backend organizations while maintaining engineering excellence.
• Develop future engineering leaders.
• Continuously improve backend methodologies and organizational capability.

Why Join?

This is an opportunity to lead one of the industry's most critical backend engineering organizations, with executive ownership of global RTL-to-GDSII execution for next-generation HPC and advanced semiconductor products.

You will shape not only the delivery of complex silicon programs but also the engineering organization, execution model, and technical strategy that enable future innovation at scale.

If you're passionate about leading world-class engineering organizations and delivering cutting-edge semiconductor products, we'd love to hear from you.

This is an on-site position based in Austin, TX. Candidates willing to relocate are welcome to apply. The company offers a competitive sign-on bonus for successful hires.