SerDes Architect and Design Engineer
Chelsea Search Group, Inc.
SerDes Architect and Design Engineer Responsibilities :
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets Required Skills & Experience :
• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Strong communication and documentation skills
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets Required Skills & Experience :
• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Strong communication and documentation skills
Vacancy posted 1 day ago
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