Senior RTL Verification Engineer - UVM/SystemVerilog

Delos Data Inc is seeking an experienced RTL Verification Engineer to ensure functionality and quality of complex digital designs across ASIC/FPGA platforms. You will build robust verification environments, run coverage-driven plans, and collaborate closely with RTL designers to deliver reliable silicon. The ideal candidate will have deep hands-on SystemVerilog/UVM experience, modern verification workflows, and the ability to drive verification efforts from planning through closure. #J-18808-Ljbffr